upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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177 lines
6.5 KiB
177 lines
6.5 KiB
/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP24XX_MEM_H_
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#define _OMAP24XX_MEM_H_
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#define SDRC_CS0_OSET 0x0
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#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
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#ifndef __ASSEMBLY__
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/* struct's for holding data tables for current boards, they are getting used
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early in init when NO global access are there */
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struct sdrc_data_s {
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u32 sdrc_sharing;
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u32 sdrc_mdcfg_0_ddr;
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u32 sdrc_mdcfg_0_sdr;
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u32 sdrc_actim_ctrla_0;
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u32 sdrc_actim_ctrlb_0;
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u32 sdrc_rfr_ctrl;
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u32 sdrc_mr_0_ddr;
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u32 sdrc_mr_0_sdr;
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u32 sdrc_dlla_ctrl;
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u32 sdrc_dllb_ctrl;
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} /*__attribute__ ((packed))*/;
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typedef struct sdrc_data_s sdrc_data_t;
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typedef enum {
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STACKED = 0,
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IP_DDR = 1,
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COMBO_DDR = 2,
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IP_SDR = 3,
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} mem_t;
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#endif
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/* Slower full frequency range default timings for x32 operation*/
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#define H4_2420_SDRC_SHARING 0x00000100
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#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
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#define H4_2420_SDRC_MR_0_SDR 0x00000031
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#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
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#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
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#define H4_2420_SDRC_MR_0_DDR 0x00000032
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#ifndef CONFIG_OPTIMIZE_DDR
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# define H4_2420_SDRC_ACTIM_CTRLA_0 0x9bead909
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# define H4_2420_SDRC_ACTIM_CTRLB_0 0x00000014
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# define H4_2420_SDRC_RFR_CTRL_ES1 0x00002401
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# define H4_2420_SDRC_RFR_CTRL 0x0002da01
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#endif
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#define H4_2420_SDRC_DLLA_CTRL 0x00007307 /* load value at 100Mhz */
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#define H4_2420_SDRC_DLLB_CTRL 0x00007307
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#define H4_2422_SDRC_SHARING 0x00004b00
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#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */
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#ifndef CONFIG_OPTIMIZE_DDR
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# define H4_2422_SDRC_ACTIM_CTRLA_0 0x9BEAD909
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# define H4_2422_SDRC_ACTIM_CTRLB_0 0x00000020
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# define H4_2422_SDRC_RFR_CTRL_ES1 0x00002401
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# define H4_2422_SDRC_RFR_CTRL 0x0002da01
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#endif
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#define H4_2422_SDRC_MR_0_DDR 0x00000032
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#define H4_2422_SDRC_DLLA_CTRL 0x00007307
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#define H4_2422_SDRC_DLLB_CTRL 0x00007307
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/* optimized timings */
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#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
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#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
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#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settigs */
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#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
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#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 /* this is not optimal yet */
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#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
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#ifdef CONFIG_OPTIMIZE_DDR
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# ifdef PRCM_CONFIG_II
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# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
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# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
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# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_100MHz
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# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
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# elif PRCM_CONFIG_III
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# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
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# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
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# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_133MHz
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# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
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# endif
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# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_2420_SDRC_ACTIM_CTRLA_0
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# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_2420_SDRC_ACTIM_CTRLB_0
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# define H4_2422_SDRC_RFR_CTRL_ES1 H4_2420_SDRC_RFR_CTRL_ES1
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# define H4_2422_SDRC_RFR_CTRL H4_2420_SDRC_RFR_CTRL
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#endif
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/* GPMC settings */
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#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
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#ifdef CFG_NAND_BOOT
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#define H4_24XX_GPMC_CONFIG1_0 0x0
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#define H4_24XX_GPMC_CONFIG2_0 0x00141400
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#define H4_24XX_GPMC_CONFIG3_0 0x00141400
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#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
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#define H4_24XX_GPMC_CONFIG5_0 0x010C1414
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#define H4_24XX_GPMC_CONFIG6_0 0x00000A80
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#else
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#define H4_24XX_GPMC_CONFIG1_0 0x3
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#define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
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#define H4_24XX_GPMC_CONFIG3_0 0x00050502
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#define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
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#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
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#endif
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#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
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#define H4_24XX_GPMC_CONFIG1_1 0x00011000
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#define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
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#define H4_24XX_GPMC_CONFIG3_1 0x00080802
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#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
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#define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
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#define H4_24XX_GPMC_CONFIG6_1 0x000003C2
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#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
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#endif
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#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
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#ifdef CFG_NAND_BOOT
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#define H4_24XX_GPMC_CONFIG1_0 0x0
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#define H4_24XX_GPMC_CONFIG2_0 0x00141400
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#define H4_24XX_GPMC_CONFIG3_0 0x00141400
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#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
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#define H4_24XX_GPMC_CONFIG5_0 0x010C1414
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#define H4_24XX_GPMC_CONFIG6_0 0x00000A80
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#else
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#define H4_24XX_GPMC_CONFIG1_0 0x3
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#define H4_24XX_GPMC_CONFIG2_0 0x00151501
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#define H4_24XX_GPMC_CONFIG3_0 0x00060602
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#define H4_24XX_GPMC_CONFIG4_0 0x10081008
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#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
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#define H4_24XX_GPMC_CONFIG6_0 0x000004c4
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#endif
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#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
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#define H4_24XX_GPMC_CONFIG1_1 0x00011000
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#define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
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#define H4_24XX_GPMC_CONFIG3_1 0x00080803
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#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
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#define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
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#define H4_24XX_GPMC_CONFIG6_1 0x000004C4
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#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
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#endif
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#ifdef CONFIG_APTIX /* SDRC-SDR for Aptix x16 */
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#define VAL_H4_SDRC_SHARING_16 0x00002400 /* No-Tristate, 16bit on D31-D16, CS1=dont care */
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#define VAL_H4_SDRC_SHARING 0x00000100
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#define VAL_H4_SDRC_MCFG_0_16 0x00901000 /* SDR-SDRAM,External,x16 bit */
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#define VAL_H4_SDRC_MCFG_0 0x01702011
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#define VAL_H4_SDRC_MR_0 0x00000029 /* Burst=2, Serial Mode, CAS 3*/
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#define VAL_H4_SDRC_RFR_CTRL_0 0x00001703 /* refresh time */
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#define VAL_H4_SDRC_DCDL2_CTRL 0x5A59B485
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#endif
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#endif
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