upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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212 lines
5.5 KiB
212 lines
5.5 KiB
/*
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* U-boot - Configuration file for BF533 STAMP board
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*/
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#ifndef __CONFIG_BF533_STAMP_H__
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#define __CONFIG_BF533_STAMP_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 11059200
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 45
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 11
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#define CONFIG_MEM_SIZE 128
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#define CONFIG_EBIU_SDRRC_VAL 0x268
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#define CONFIG_EBIU_SDGCTL_VAL 0x911109
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
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#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
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/*
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* Network Settings
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*/
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_NET_MULTI
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#define CONFIG_SMC91111 1
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#define CONFIG_SMC91111_BASE 0x20300300
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#define SMC91111_EEPROM_INIT() \
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do { \
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bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
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bfin_write_FIO_FLAG_C(PF1); \
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bfin_write_FIO_FLAG_S(PF0); \
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SSYNC(); \
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} while (0)
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#define CONFIG_HOSTNAME bf533-stamp
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
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/*
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* Flash Settings
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 67
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_ALL
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/*
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* Env Storage Settings
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*/
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OFFSET 0x4000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#endif
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
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#define ENV_IS_EMBEDDED
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#else
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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#endif
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#ifdef ENV_IS_EMBEDDED
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/* WARNING - the following is hand-optimized to fit within
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* the sector before the environment sector. If it throws
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* an error during compilation remove an object here to get
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* it linked after the configuration sector.
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*/
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# define LDS_BOARD_TEXT \
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arch/blackfin/cpu/traps.o (.text .text.*); \
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arch/blackfin/cpu/interrupt.o (.text .text.*); \
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arch/blackfin/cpu/serial.o (.text .text.*); \
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common/dlmalloc.o (.text .text.*); \
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lib/crc32.o (.text .text.*); \
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. = DEFINED(env_offset) ? env_offset : .; \
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common/env_embedded.o (.text .text.*);
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#endif
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/*
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* I2C Settings
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*/
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#define CONFIG_SOFT_I2C
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#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
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#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
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/*
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* Compact Flash / IDE / ATA Settings
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*/
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/* Enabled below option for CF support */
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/* #define CONFIG_STAMP_CF */
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#if defined(CONFIG_STAMP_CF)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_DOS_PARTITION 1
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
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#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
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#define CONFIG_SYS_ATA_STRIDE 2
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#undef CONFIG_EBIU_AMBCTL1_VAL
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#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
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#endif
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/*
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* Misc Settings
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*/
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 0
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/* FLASH/ETHERNET uses the same async bank */
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#define SHARED_RESOURCES 1
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/* define to enable boot progress via leds */
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/* #define CONFIG_SHOW_BOOT_PROGRESS */
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/* define to enable run status via led */
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/* #define CONFIG_STATUS_LED */
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#ifdef CONFIG_STATUS_LED
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#define CONFIG_GPIO_LED
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#define CONFIG_BOARD_SPECIFIC_LED
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/* use LED0 to indicate booting/alive */
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#define STATUS_LED_BOOT 0
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#define STATUS_LED_BIT GPIO_PF2
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#define STATUS_LED_STATE STATUS_LED_ON
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#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
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/* use LED1 to indicate crash */
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#define STATUS_LED_CRASH 1
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#define STATUS_LED_BIT1 GPIO_PF3
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#define STATUS_LED_STATE1 STATUS_LED_ON
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#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
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/* #define STATUS_LED_BIT2 GPIO_PF4 */
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#endif
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/* define to enable splash screen support */
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/* #define CONFIG_VIDEO */
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif
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