upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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183 lines
6.0 KiB
183 lines
6.0 KiB
/*
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* bluestone.h - configuration for Bluestone (APM821XX)
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*
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* Copyright (c) 2010, Applied Micro Circuits Corporation
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* Author: Tirumala R Marri <tmarri@apm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_APM821XX 1 /* APM821XX series */
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#define CONFIG_HOSTNAME bluestone
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_440 1
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
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#endif
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#include "amcc-common.h"
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#define CONFIG_SYS_CLK_FREQ 50000000
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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/* EBC stuff */
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/* later mapped to this addr */
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#define CONFIG_SYS_FLASH_BASE 0xFFF00000
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#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */
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/* EBC Boot Space: 0xFF000000 */
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
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#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */
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#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
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#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/
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#define CONFIG_SYS_SRAM_SIZE (256 << 10)
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/*
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* Initial RAM & stack pointer (placed in OCM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
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#define CONFIG_SYS_INIT_RAM_END (4 << 10)
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#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Environment
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*/
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/*
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* Define here the location of the environment variables (FLASH).
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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/*
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* FLASH related
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
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/* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 80
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/* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
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/* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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/* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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/* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/* SDRAM */
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */
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#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
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#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
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#define CONFIG_DDR_ECC 1 /* with ECC support */
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */
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/* I2C bootstrap EEPROM */
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
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#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
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/*
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* Ethernet
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*/
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII
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#define CONFIG_HAS_ETH0
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/* PHY address, See schematics */
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#define CONFIG_PHY_ADDR 0x1f
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/* reset phy upon startup */
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#define CONFIG_PHY_RESET 1
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/* Include GbE speed/duplex detection */
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#define CONFIG_PHY_GIGE 1
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#define CONFIG_PHY_DYNAMIC_ANEG 1
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/*
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* External Bus Controller (EBC) Setup
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**/
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#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \
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EBC_CFG_PTD_ENABLE | \
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EBC_CFG_RTC_2048PERCLK | \
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EBC_CFG_ATC_HI | \
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EBC_CFG_DTC_HI | \
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EBC_CFG_CTC_HI | \
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EBC_CFG_OEO_PREVIOUS)
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/* NOR Flash */
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#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(64) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(1) | \
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EBC_BXAP_OEN_ENCODE(2) | \
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EBC_BXAP_WBN_ENCODE(2) | \
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EBC_BXAP_WBF_ENCODE(2) | \
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EBC_BXAP_TH_ENCODE(7) | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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/* Peripheral Bank Configuration Register - EBC_BxCR */
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#define CONFIG_SYS_EBC_PB0CR \
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(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
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EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_8BIT)
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#endif /* __CONFIG_H */
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