upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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367 lines
11 KiB
367 lines
11 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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* Ilko Iliev <www.ronetix.at>
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*
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* Configuation settings for the RONETIX PM9263 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* ARM asynchronous clock */
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#define AT91_CPU_NAME "AT91SAM9263"
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#define CONFIG_DISPLAY_BOARDINFO
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#define MASTER_PLL_DIV 15
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#define MASTER_PLL_MUL 162
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#define MAIN_PLL_DIV 2 /* 2 or 4 */
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#define AT91_MAIN_CLOCK 18432000
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
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#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* clocks */
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#define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */
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#define CONFIG_SYS_PLLAR_VAL \
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(0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#if (MAIN_PLL_DIV == 2)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL 0x00000100
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL 0x00000102
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#else
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/* PCK/4 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL 0x00000200
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/* PCK/4 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL 0x00000202
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#endif
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
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/* no pull-up for D[31:16] */
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#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
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/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
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#define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A
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/* EBI1_CSA, 3.3v, no pull-ups */
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#define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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#define CONFIG_SYS_SDRC_MR_VAL1 0
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/* SDRAMC_TR - Refresh Timer register */
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#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
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#define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/
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/* Memory Device Register -> SDRAM */
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#define CONFIG_SYS_SDRC_MDR_VAL 0
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#define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */
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#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */
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#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */
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#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */
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#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
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/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
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#define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
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#define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
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#define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
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#define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
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/* setup SMC1, CS0 (PSRAM) - 16-bit */
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#define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */
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#define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */
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#define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */
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#define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */
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#define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */
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/* Watchdog */
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#define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
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/* */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#undef CONFIG_SKIP_LOWLEVEL_INIT
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#undef CONFIG_SKIP_RELOCATE_UBOOT
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#define CONFIG_USER_LOWLEVEL_INIT 1
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/*
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* Hardware drivers
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*/
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#define CONFIG_ATMEL_USART 1
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#define CONFIG_USART3 1 /* USART 3 is DBGU */
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/* LCD */
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#define CONFIG_LCD 1
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#define LCD_BPP LCD_COLOR8
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#define CONFIG_LCD_LOGO 1
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#undef LCD_TEST_PATTERN
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#define CONFIG_LCD_INFO 1
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#define CONFIG_LCD_INFO_BELOW_LOGO 1
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#define CONFIG_SYS_WHITE_ON_BLACK 1
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#define CONFIG_ATMEL_LCD 1
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#define CONFIG_ATMEL_LCD_BGR555 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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#define CONFIG_LCD_IN_PSRAM 1
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/* LED */
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#define CONFIG_AT91_LED
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#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
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#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
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#define CONFIG_BOOTDELAY 3
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE 1
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#define CONFIG_BOOTP_BOOTPATH 1
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#define CONFIG_BOOTP_GATEWAY 1
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#define CONFIG_BOOTP_HOSTNAME 1
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_AUTOSCRIPT
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_PING 1
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#define CONFIG_CMD_DHCP 1
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#define CONFIG_CMD_NAND 1
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#define CONFIG_CMD_USB 1
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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/* DataFlash */
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#define CONFIG_ATMEL_DATAFLASH_SPI
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#define CONFIG_HAS_DATAFLASH 1
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#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
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#define AT91_SPI_CLK 15000000
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#define DATAFLASH_TCSS (0x1a << 16)
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#define DATAFLASH_TCHS (0x1 << 24)
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/* NOR flash, if populated */
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define PHYS_FLASH_1 0x10000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
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#endif
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#define CONFIG_CMD_JFFS2 1
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#define CONFIG_JFFS2_CMDLINE 1
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#define CONFIG_JFFS2_NAND 1
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#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
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#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
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/* PSRAM */
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#define PHYS_PSRAM 0x70000000
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#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
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/* Ethernet */
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#define CONFIG_MACB 1
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#define CONFIG_RMII 1
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#define CONFIG_NET_MULTI 1
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_RESET_PHY_R 1
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END 0x23e00000
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#define CONFIG_SYS_USE_FLASH 1
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#undef CONFIG_SYS_USE_DATAFLASH
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#undef CONFIG_SYS_USE_NANDFLASH
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#ifdef CONFIG_SYS_USE_DATAFLASH
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/* bootstrap + u-boot + env + linux in dataflash on CS0 */
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#define CONFIG_ENV_IS_IN_DATAFLASH
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#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
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#define CONFIG_ENV_OFFSET 0x4200
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#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SIZE 0x4200
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#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
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#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
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"root=/dev/mtdblock0 " \
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"mtdparts=at91_nand:-(root) "\
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"rw rootfstype=jffs2"
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#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
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/* bootstrap + u-boot + env + linux in nandflash */
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_OFFSET_REDUND 0x80000
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#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
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#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
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#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
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"root=/dev/mtdblock5 " \
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"mtdparts=at91_nand:" \
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"128k(bootstrap)ro," \
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"256k(uboot)ro," \
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"128k(env1)ro," \
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"128k(env2)ro," \
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"2M(linux)," \
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"-(root) " \
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"rw rootfstype=jffs2"
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#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_OVERWRITE 1
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/* JFFS Partition offset set */
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#define CONFIG_SYS_JFFS2_FIRST_BANK 0
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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/* 512k reserved for u-boot */
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#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
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#define CONFIG_BOOTCOMMAND "run flashboot"
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#define CONFIG_ROOTPATH /ronetix/rootfs
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#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
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#define CONFIG_CON_ROT "fbcon=rotate:3 "
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#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
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CONFIG_CON_ROT
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
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#define MTDPARTS_DEFAULT \
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"mtdparts=physmap-flash.0:" \
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"256k(u-boot)ro," \
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"64k(u-boot-env)ro," \
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"1408k(kernel)," \
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"-(rootfs);" \
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"nand:-(nand)"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"partition=nand0,0\0" \
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"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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CONFIG_CON_ROT \
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"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
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":$(hostname):eth0:off\0" \
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"ramboot=tftpboot 0x22000000 vmImage;" \
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"run ramargs;run addip;bootm 22000000\0" \
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"nfsboot=tftpboot 0x22000000 vmImage;" \
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"run nfsargs;run addip;bootm 22000000\0" \
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"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
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""
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#else
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#error "Undefined memory device"
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_SYS_PROMPT "u-boot-pm9263> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
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#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ not supported
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#endif
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#endif
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