upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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125 lines
3.4 KiB
125 lines
3.4 KiB
/*
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* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#ifdef CONFIG_VCT_PLATINUMAVC
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#define UART_1_BASE 0xBDC30000
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#else
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#define UART_1_BASE 0xBF89C000
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#endif
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#define UART_RBR_OFF 0x00 /* receiver buffer reg */
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#define UART_THR_OFF 0x00 /* transmit holding reg */
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#define UART_DLL_OFF 0x00 /* divisor latch low reg */
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#define UART_IER_OFF 0x04 /* interrupt enable reg */
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#define UART_DLH_OFF 0x04 /* receiver buffer reg */
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#define UART_FCR_OFF 0x08 /* fifo control register */
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#define UART_LCR_OFF 0x0c /* line control register */
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#define UART_MCR_OFF 0x10 /* modem control register */
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#define UART_LSR_OFF 0x14 /* line status register */
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#define UART_MSR_OFF 0x18 /* modem status register */
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#define UART_SCR_OFF 0x1c /* scratch pad register */
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#define UART_RCV_DATA_RDY 0x01 /* Data Received */
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#define UART_XMT_HOLD_EMPTY 0x20
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#define UART_TRANSMIT_EMPTY 0x40
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/* 7 bit on line control reg. enalbing rw to dll and dlh */
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#define UART_LCR_DLAB 0x0080
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#define UART___9600_BDR 0x84
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#define UART__19200_BDR 0x42
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#define UART_115200_BDR 0x08
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#define UART_DIS_ALL_INTER 0x00 /* disable all interrupts */
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#define UART_5DATA_BITS 0x0000 /* 5 [bits] 1.5 bits 2 */
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#define UART_6DATA_BITS 0x0001 /* 6 [bits] 1 bits 2 */
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#define UART_7DATA_BITS 0x0002 /* 7 [bits] 1 bits 2 */
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#define UART_8DATA_BITS 0x0003 /* 8 [bits] 1 bits 2 */
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static void vct_uart_set_baud_rate(u32 address, u32 dh, u32 dl)
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{
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u32 val = __raw_readl(UART_1_BASE + UART_LCR_OFF);
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/* set 7 bit on 1 */
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val |= UART_LCR_DLAB;
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__raw_writel(val, UART_1_BASE + UART_LCR_OFF);
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__raw_writel(dl, UART_1_BASE + UART_DLL_OFF);
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__raw_writel(dh, UART_1_BASE + UART_DLH_OFF);
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/* set 7 bit on 0 */
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val &= ~UART_LCR_DLAB;
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__raw_writel(val, UART_1_BASE + UART_LCR_OFF);
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return;
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}
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int serial_init(void)
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{
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__raw_writel(UART_DIS_ALL_INTER, UART_1_BASE + UART_IER_OFF);
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vct_uart_set_baud_rate(UART_1_BASE, 0, UART_115200_BDR);
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__raw_writel(UART_8DATA_BITS, UART_1_BASE + UART_LCR_OFF);
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return 0;
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}
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void serial_setbrg(void)
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{
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/*
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* Baudrate change not supported currently, fixed to 115200 baud
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*/
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}
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void serial_putc(const char c)
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{
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if (c == '\n')
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serial_putc('\r');
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while (!(UART_XMT_HOLD_EMPTY & __raw_readl(UART_1_BASE + UART_LSR_OFF)))
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;
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__raw_writel(c, UART_1_BASE + UART_THR_OFF);
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}
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void serial_puts(const char *s)
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{
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while (*s)
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serial_putc(*s++);
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}
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int serial_getc(void)
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{
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while (!(UART_RCV_DATA_RDY & __raw_readl(UART_1_BASE + UART_LSR_OFF)))
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;
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return __raw_readl(UART_1_BASE + UART_RBR_OFF) & 0xff;
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}
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int serial_tstc(void)
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{
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if (!(UART_RCV_DATA_RDY & __raw_readl(UART_1_BASE + UART_LSR_OFF)))
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return 0;
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return 1;
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}
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