upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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48 lines
1.5 KiB
48 lines
1.5 KiB
/*
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* GTBUS initialisation for sun9i
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*
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* (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
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* Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gtbus_sun9i.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_SPL_BUILD
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void gtbus_init(void)
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{
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struct sunxi_gtbus_reg * const gtbus =
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(struct sunxi_gtbus_reg *)SUNXI_GTBUS_BASE;
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/*
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* We use the same setting that Allwinner used in Boot0 for now.
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* It may be advantageous to adjust these for various workloads
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* (e.g. headless use cases that focus on IO throughput).
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*/
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writel((GT_PRIO_HIGH << GT_PORT_FE0) |
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(GT_PRIO_HIGH << GT_PORT_BE1) |
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(GT_PRIO_HIGH << GT_PORT_BE2) |
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(GT_PRIO_HIGH << GT_PORT_IEP0) |
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(GT_PRIO_HIGH << GT_PORT_FE1) |
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(GT_PRIO_HIGH << GT_PORT_BE0) |
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(GT_PRIO_HIGH << GT_PORT_FE2) |
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(GT_PRIO_HIGH << GT_PORT_IEP1),
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>bus->mst_read_prio_cfg[0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE1]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE2]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE1]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE2]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP1]);
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}
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#endif
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