upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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552 lines
18 KiB
552 lines
18 KiB
/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* mpc8544ds board configuration file
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
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#define CONFIG_MPC8544 1
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#define CONFIG_MPC8544DS 1
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#define CONFIG_PCI 1 /* Enable PCI/PCIE */
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#define CONFIG_PCI1 1 /* PCI controller 1 */
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#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
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#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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* assume this is the AMD flash associated with the CDS board.
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* This allows booting from a promjet.
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*/
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#define CONFIG_ASSUME_AMD_FLASH
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#ifndef __ASSEMBLY__
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extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
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/* DDR Setup */
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#define CONFIG_FSL_DDR2
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#define CONFIG_DDR_SPD
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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/* I2C addresses of SPD EEPROMs */
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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/* Make sure required options are set */
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#ifndef CONFIG_SPD_EEPROM
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#error ("CONFIG_SPD_EEPROM is required")
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
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*
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* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
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*
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* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
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*
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* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
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* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
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*
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* Localbus cacheable
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*
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* 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
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* 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
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*
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* Localbus non-cacheable
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*
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
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*
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*/
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
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#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
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#define CONFIG_SYS_BR0_PRELIM 0xff801001
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#define CONFIG_SYS_BR1_PRELIM 0xfe801001
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#define CONFIG_SYS_OR0_PRELIM 0xff806e65
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#define CONFIG_SYS_OR1_PRELIM 0xff806e65
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
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#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
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#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
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#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
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#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
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#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
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#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
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#define PIXIS_ID 0x0 /* Board ID at offset 0 */
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#define PIXIS_VER 0x1 /* Board version at offset 1 */
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#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
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#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
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#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
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* register */
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#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
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#define PIXIS_VCTL 0x10 /* VELA Control Register */
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#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
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#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
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#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
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#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
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#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
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#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
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#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
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#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
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#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
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#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
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#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
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#define PIXIS_VSPEED2_TSEC1SER 0x2
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#define PIXIS_VSPEED2_TSEC3SER 0x1
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#define PIXIS_VCFGEN1_TSEC1SER 0x20
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#define PIXIS_VCFGEN1_TSEC3SER 0x40
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#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
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#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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#define CONFIG_SYS_64BIT_STRTOUL 1
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#define CONFIG_SYS_64BIT_VSPRINTF 1
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/* I2C */
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CONFIG_SYS_I2C_OFFSET 0x3100
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
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#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
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#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
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#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
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#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
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#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, Slot 1, tgtid 1, Base address 9000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, Slot 2,tgtid 2, Base address a000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/* controller 3, direct to uli, tgtid 3, Base address b000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
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#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
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#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
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#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
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#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
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#if defined(CONFIG_PCI)
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/*PCIE video card used*/
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#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
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/*PCI video card used*/
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/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
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/* video */
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#define CONFIG_VIDEO
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#if defined(CONFIG_VIDEO)
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#define CONFIG_BIOSEMU
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_ATI_RADEON_FB
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#define CONFIG_VIDEO_LOGO
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/*#define CONFIG_CONSOLE_CURSOR*/
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
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#endif
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#define CONFIG_RTL8139
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#ifndef CONFIG_PCI_PNP
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#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
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#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
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#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
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#endif
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SCSI_AHCI
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#ifdef CONFIG_SCSI_AHCI
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#define CONFIG_SATA_ULI5288
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
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#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
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#endif /* SCSCI */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define CONFIG_PIXIS_SGMII_CMD
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#define CONFIG_FSL_SGMII_RISER 1
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#define SGMII_RISER_PHY_OFFSET 0x1c
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#define TSEC1_PHY_ADDR 0
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#define TSEC3_PHY_ADDR 1
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
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#define CONFIG_ENV_ADDR 0xfff80000
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
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#endif
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_SETEXPR
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_SCSI
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#define CONFIG_CMD_EXT2
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 16 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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/* The mac addresses for all ethernet interface */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
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#endif
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#define CONFIG_IPADDR 192.168.1.251
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#define CONFIG_HOSTNAME 8544ds_unknown
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#define CONFIG_ROOTPATH /nfs/mpc85xx
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#define CONFIG_BOOTFILE 8544ds/uImage.uboot
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#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
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#define CONFIG_SERVERIP 192.168.1.1
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#define CONFIG_GATEWAYIP 192.168.1.1
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
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#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
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"erase " MK_STR(TEXT_BASE) " +$filesize; " \
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"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
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"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
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"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=8544ds/ramdisk.uboot\0" \
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"fdtaddr=c00000\0" \
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"fdtfile=8544ds/mpc8544ds.dtb\0" \
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"bdev=sda3\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs root=/dev/$bdev rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#endif /* __CONFIG_H */
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