upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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553 lines
13 KiB
553 lines
13 KiB
/*
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* (C) Copyright 2007-2008
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* Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <asm/processor.h>
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#if defined(CONFIG_LOGBUFFER)
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#include <logbuff.h>
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#endif
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#include "pmc440.h"
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int is_monarch(void);
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int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
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uchar *buffer, unsigned cnt);
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int eeprom_write_enable(unsigned dev_addr, int state);
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_BSP)
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static int got_fifoirq;
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static int got_hcirq;
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int fpga_interrupt(u32 arg)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
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int rc = -1; /* not for us */
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u32 status = FPGA_IN32(&fpga->status);
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/* check for interrupt from fifo module */
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if (status & STATUS_FIFO_ISF) {
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/* disable this int source */
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FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
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rc = 0;
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got_fifoirq = 1; /* trigger backend */
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}
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if (status & STATUS_HOST_ISF) {
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FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
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rc = 0;
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got_hcirq = 1;
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}
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return rc;
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}
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int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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got_hcirq = 0;
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FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
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FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
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irq_install_handler(IRQ0_FPGA,
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(interrupt_handler_t *)fpga_interrupt,
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fpga);
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FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
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while (!got_hcirq) {
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/* Abort if ctrl-c was pressed */
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if (ctrlc()) {
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puts("\nAbort\n");
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break;
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}
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}
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if (got_hcirq)
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printf("Got interrupt!\n");
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FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
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irq_free_handler(IRQ0_FPGA);
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return 0;
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}
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U_BOOT_CMD(
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waithci, 1, 1, do_waithci,
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"Wait for host control interrupt",
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""
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);
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void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
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{
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u32 ctrl;
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while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
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printf("%5d %d %3d %08x",
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(*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
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FPGA_IN32(&fpga->fifo[f].data));
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if (ctrl & FIFO_OVERFLOW) {
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printf(" OVERFLOW\n");
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FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
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} else
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printf("\n");
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}
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}
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int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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int i;
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int n = 0;
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u32 ctrl, data, f;
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char str[] = "\\|/-";
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int abort = 0;
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int count = 0;
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int count2 = 0;
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switch (argc) {
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case 1:
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/* print all fifos status information */
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printf("fifo level status\n");
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printf("______________________________\n");
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for (i=0; i<FIFO_COUNT; i++) {
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ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
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printf(" %d %3d %s%s%s %s\n",
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i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
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ctrl & FIFO_FULL ? "FULL " : "",
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ctrl & FIFO_EMPTY ? "EMPTY " : "",
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ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
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ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
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}
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break;
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case 2:
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/* completely read out fifo 'n' */
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if (!strcmp(argv[1],"read")) {
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printf(" # fifo level data\n");
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printf("______________________________\n");
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for (i=0; i<FIFO_COUNT; i++)
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dump_fifo(fpga, i, &n);
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} else if (!strcmp(argv[1],"wait")) {
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got_fifoirq = 0;
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irq_install_handler(IRQ0_FPGA,
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(interrupt_handler_t *)fpga_interrupt,
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fpga);
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printf(" # fifo level data\n");
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printf("______________________________\n");
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/* enable all fifo interrupts */
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FPGA_OUT32(&fpga->hostctrl,
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HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
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for (i=0; i<FIFO_COUNT; i++) {
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/* enable interrupts from all fifos */
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FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
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}
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while (1) {
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/* wait loop */
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while (!got_fifoirq) {
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count++;
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if (!(count % 100)) {
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count2++;
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putc(0x08); /* backspace */
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putc(str[count2 % 4]);
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}
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/* Abort if ctrl-c was pressed */
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if ((abort = ctrlc())) {
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puts("\nAbort\n");
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break;
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}
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udelay(1000);
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}
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if (abort)
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break;
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/* simple fifo backend */
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if (got_fifoirq) {
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for (i=0; i<FIFO_COUNT; i++)
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dump_fifo(fpga, i, &n);
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got_fifoirq = 0;
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/* unmask global fifo irq */
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FPGA_OUT32(&fpga->hostctrl,
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HOSTCTRL_FIFOIE_GATE |
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HOSTCTRL_FIFOIE_FLAG);
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}
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}
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/* disable all fifo interrupts */
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FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
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for (i=0; i<FIFO_COUNT; i++)
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FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
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irq_free_handler(IRQ0_FPGA);
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} else {
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printf("Usage:\nfifo %s\n", cmdtp->help);
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return 1;
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}
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break;
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case 4:
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case 5:
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if (!strcmp(argv[1],"write")) {
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/* get fifo number or fifo address */
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f = simple_strtoul(argv[2], NULL, 16);
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/* data paramter */
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data = simple_strtoul(argv[3], NULL, 16);
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/* get optional count parameter */
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n = 1;
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if (argc >= 5)
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n = (int)simple_strtoul(argv[4], NULL, 10);
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if (f < FIFO_COUNT) {
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printf("writing %d x %08x to fifo %d\n",
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n, data, f);
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for (i=0; i<n; i++)
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FPGA_OUT32(&fpga->fifo[f].data, data);
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} else {
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printf("writing %d x %08x to fifo port at "
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"address %08x\n",
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n, data, f);
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for (i=0; i<n; i++)
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out_be32((void *)f, data);
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}
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} else {
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printf("Usage:\nfifo %s\n", cmdtp->help);
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return 1;
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}
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break;
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default:
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printf("Usage:\nfifo %s\n", cmdtp->help);
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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fifo, 5, 1, do_fifo,
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"Fifo module operations",
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"wait\nfifo read\n"
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"fifo write fifo(0..3) data [cnt=1]\n"
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"fifo write address(>=4) data [cnt=1]\n"
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" - without arguments: print all fifo's status\n"
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" - with 'wait' argument: interrupt driven read from all fifos\n"
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" - with 'read' argument: read current contents from all fifos\n"
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" - with 'write' argument: write 'data' 'cnt' times to "
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"'fifo' or 'address'"
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);
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int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong sdsdp[5];
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ulong delay;
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int count=16;
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if (argc < 2) {
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printf("Usage:\nsbe %s\n", cmdtp->help);
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return -1;
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}
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if (argc > 1) {
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if (!strcmp(argv[1], "400")) {
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/* PLB=133MHz, PLB/PCI=3 */
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printf("Bootstrapping for 400MHz\n");
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sdsdp[0]=0x8678624e;
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sdsdp[1]=0x095fa030;
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sdsdp[2]=0x40082350;
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sdsdp[3]=0x0d050000;
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} else if (!strcmp(argv[1], "533")) {
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/* PLB=133MHz, PLB/PCI=3 */
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printf("Bootstrapping for 533MHz\n");
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sdsdp[0]=0x87788252;
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sdsdp[1]=0x095fa030;
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sdsdp[2]=0x40082350;
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sdsdp[3]=0x0d050000;
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} else if (!strcmp(argv[1], "667")) {
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/* PLB=133MHz, PLB/PCI=3 */
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printf("Bootstrapping for 667MHz\n");
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sdsdp[0]=0x8778a256;
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sdsdp[1]=0x095fa030;
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sdsdp[2]=0x40082350;
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sdsdp[3]=0x0d050000;
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} else {
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printf("Usage:\nsbe %s\n", cmdtp->help);
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return -1;
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}
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}
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if (argc > 2) {
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sdsdp[4] = 0;
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if (argv[2][0]=='1')
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sdsdp[4]=0x19750100;
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else if (argv[2][0]=='0')
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sdsdp[4]=0x19750000;
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if (sdsdp[4])
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count += 4;
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}
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if (argc > 3) {
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delay = simple_strtoul(argv[3], NULL, 10);
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if (delay > 20)
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delay = 20;
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sdsdp[4] |= delay;
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}
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printf("Writing boot EEPROM ...\n");
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if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
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0, (uchar*)sdsdp, count) != 0)
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printf("bootstrap_eeprom_write failed\n");
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else
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printf("done (dump via 'i2c md 52 0.1 14')\n");
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return 0;
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}
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U_BOOT_CMD(
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sbe, 4, 0, do_setup_bootstrap_eeprom,
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"setup bootstrap eeprom",
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"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
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);
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#if defined(CONFIG_PRAM)
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#include <environment.h>
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#include <search.h>
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#include <errno.h>
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int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 pram, nextbase, base;
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char *v;
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u32 param;
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ulong *lptr;
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env_t *envp;
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char *res;
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int len;
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v = getenv("pram");
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if (v)
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pram = simple_strtoul(v, NULL, 10);
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else {
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printf("Error: pram undefined. Please define pram in KiB\n");
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return 1;
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}
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base = gd->bd->bi_memsize;
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#if defined(CONFIG_LOGBUFFER)
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base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
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#endif
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/*
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* gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
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*/
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param = base - (pram << 10);
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printf("PARAM: @%08x\n", param);
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debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
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/* clear entire PA ram */
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memset((void*)param, 0, (pram << 10));
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/* reserve 4k for pointer field */
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nextbase = base - 4096;
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lptr = (ulong*)(base);
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/*
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* *(--lptr) = item_size;
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* *(--lptr) = base - item_base = distance from field top;
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*/
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/* env is first (4k aligned) */
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nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
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envp = (env_t *)nextbase;
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res = (char *)envp->data;
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len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
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if (len < 0) {
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error("Cannot export environment: errno = %d\n", errno);
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return 1;
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}
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envp->crc = crc32(0, envp->data, ENV_SIZE);
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*(--lptr) = CONFIG_ENV_SIZE; /* size */
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*(--lptr) = base - nextbase; /* offset | type=0 */
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/* free section */
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*(--lptr) = nextbase - param; /* size */
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*(--lptr) = (base - param) | 126; /* offset | type=126 */
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/* terminate pointer field */
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*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
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*(--lptr) = 0; /* offset=0 -> terminator */
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return 0;
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}
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U_BOOT_CMD(
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painit, 1, 1, do_painit,
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"prepare PciAccess system",
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""
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);
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#endif /* CONFIG_PRAM */
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int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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in_be32((void*)CONFIG_SYS_RESET_BASE);
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return 0;
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}
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U_BOOT_CMD(
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selfreset, 1, 1, do_selfreset,
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"assert self-reset# signal",
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""
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);
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int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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/* requiers bootet FPGA and PLD_IOEN_N active */
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if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
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printf("Error: resetout requires a bootet FPGA\n");
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return -1;
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}
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if (argc > 1) {
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if (argv[1][0] == '0') {
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/* assert */
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printf("PMC-RESETOUT# asserted\n");
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FPGA_OUT32(&fpga->hostctrl,
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HOSTCTRL_PMCRSTOUT_GATE);
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} else {
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/* deassert */
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printf("PMC-RESETOUT# deasserted\n");
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FPGA_OUT32(&fpga->hostctrl,
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HOSTCTRL_PMCRSTOUT_GATE |
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HOSTCTRL_PMCRSTOUT_FLAG);
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}
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} else {
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printf("PMC-RESETOUT# is %s\n",
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FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
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"inactive" : "active");
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}
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return 0;
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}
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U_BOOT_CMD(
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resetout, 2, 1, do_resetout,
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"assert PMC-RESETOUT# signal",
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""
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);
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int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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if (is_monarch()) {
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printf("This command is only supported in non-monarch mode\n");
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return -1;
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}
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if (argc > 1) {
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if (argv[1][0] == '0') {
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/* assert */
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printf("inta# asserted\n");
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out_be32((void*)GPIO1_TCR,
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in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
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} else {
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/* deassert */
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printf("inta# deasserted\n");
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out_be32((void*)GPIO1_TCR,
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in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
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}
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} else {
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printf("inta# is %s\n",
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in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
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"active" : "inactive");
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}
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return 0;
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}
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U_BOOT_CMD(
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inta, 2, 1, do_inta,
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"Assert/Deassert or query INTA# state in non-monarch mode",
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""
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);
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|
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/* test-only */
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int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong pciaddr;
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if (argc > 1) {
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pciaddr = simple_strtoul(argv[1], NULL, 16);
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pciaddr &= 0xf0000000;
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/* map PCI address at 0xc0000000 in PLB space */
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/* PMM1 Mask/Attribute - disabled b4 setting */
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out32r(PCIL0_PMM1MA, 0x00000000);
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/* PMM1 Local Address */
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out32r(PCIL0_PMM1LA, 0xc0000000);
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/* PMM1 PCI Low Address */
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out32r(PCIL0_PMM1PCILA, pciaddr);
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/* PMM1 PCI High Address */
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out32r(PCIL0_PMM1PCIHA, 0x00000000);
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|
/* 256MB + No prefetching, and enable region */
|
|
out32r(PCIL0_PMM1MA, 0xf0000001);
|
|
} else {
|
|
printf("Usage:\npmm %s\n", cmdtp->help);
|
|
}
|
|
return 0;
|
|
}
|
|
U_BOOT_CMD(
|
|
pmm, 2, 1, do_pmm,
|
|
"Setup pmm[1] registers",
|
|
"<pciaddr> (pciaddr will be aligned to 256MB)"
|
|
);
|
|
|
|
#if defined(CONFIG_SYS_EEPROM_WREN)
|
|
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
int query = argc == 1;
|
|
int state = 0;
|
|
|
|
if (query) {
|
|
/* Query write access state. */
|
|
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
|
|
if (state < 0) {
|
|
puts("Query of write access state failed.\n");
|
|
} else {
|
|
printf("Write access for device 0x%0x is %sabled.\n",
|
|
CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
|
state = 0;
|
|
}
|
|
} else {
|
|
if ('0' == argv[1][0]) {
|
|
/* Disable write access. */
|
|
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
|
|
} else {
|
|
/* Enable write access. */
|
|
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
|
|
}
|
|
if (state < 0) {
|
|
puts("Setup of write access state failed.\n");
|
|
}
|
|
}
|
|
|
|
return state;
|
|
}
|
|
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
|
"Enable / disable / query EEPROM write access",
|
|
""
|
|
);
|
|
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
|
|
|
|
#endif /* CONFIG_CMD_BSP */
|
|
|