upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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125 lines
3.2 KiB
125 lines
3.2 KiB
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <dm/device.h>
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#include <mmc.h>
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#include <sdhci.h>
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/* HRS - Host Register Set (specific to Cadence) */
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#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
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#define SDHCI_CDNS_HRS04_ACK BIT(26)
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#define SDHCI_CDNS_HRS04_RD BIT(25)
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#define SDHCI_CDNS_HRS04_WR BIT(24)
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#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12
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#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
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#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
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/* SRS - Slot Register Set (SDHCI-compatible) */
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#define SDHCI_CDNS_SRS_BASE 0x200
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/* PHY */
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#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
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#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
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#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
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#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
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#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
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#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
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struct sdhci_cdns_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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void __iomem *hrs_addr;
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};
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static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
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u8 addr, u8 data)
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{
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void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
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u32 tmp;
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tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
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(addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
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writel(tmp, reg);
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tmp |= SDHCI_CDNS_HRS04_WR;
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writel(tmp, reg);
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tmp &= ~SDHCI_CDNS_HRS04_WR;
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writel(tmp, reg);
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}
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static void sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat)
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{
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sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_HS, 4);
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sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4);
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sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9);
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sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2);
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sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3);
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}
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static int sdhci_cdns_bind(struct udevice *dev)
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{
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struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static int sdhci_cdns_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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fdt_addr_t base;
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int ret;
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base = dev_get_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
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if (!plat->hrs_addr)
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return -ENOMEM;
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host->name = dev->name;
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host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
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host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
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sdhci_cdns_phy_init(plat);
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
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if (ret)
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return ret;
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upriv->mmc = &plat->mmc;
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host->mmc = &plat->mmc;
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host->mmc->priv = host;
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return sdhci_probe(dev);
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}
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static const struct udevice_id sdhci_cdns_match[] = {
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{ .compatible = "socionext,uniphier-sd4hc" },
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{ .compatible = "cdns,sd4hc" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(sdhci_cdns) = {
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.name = "sdhci-cdns",
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.id = UCLASS_MMC,
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.of_match = sdhci_cdns_match,
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.bind = sdhci_cdns_bind,
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.probe = sdhci_cdns_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
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.ops = &sdhci_ops,
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};
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