upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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545 lines
14 KiB
545 lines
14 KiB
/*
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* ADI Blackfin 537 MAC Ethernet
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*
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* Copyright (c) 2005 Analog Device, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/blackfin.h>
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#include <net.h>
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#include <command.h>
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#include <malloc.h>
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#include "ether_bf537.h"
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#ifdef CONFIG_POST
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#include <post.h>
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#endif
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#undef DEBUG_ETHERNET
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#ifdef DEBUG_ETHERNET
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#define DEBUGF(fmt,args...) printf(fmt,##args)
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#else
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#define DEBUGF(fmt,args...)
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#endif
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#if defined(CONFIG_CMD_NET)
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#define RXBUF_BASE_ADDR 0xFF900000
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#define TXBUF_BASE_ADDR 0xFF800000
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#define TX_BUF_CNT 1
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#define TOUT_LOOP 1000000
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ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
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ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
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static u16 txIdx; /* index of the current RX buffer */
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static u16 rxIdx; /* index of the current TX buffer */
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u8 SrcAddr[6];
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u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
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/* DMAx_CONFIG values at DMA Restart */
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const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 };
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#if 0
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rxdmacfg.b_DMA_EN = 1; /* enabled */
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rxdmacfg.b_WNR = 1; /* write to memory */
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rxdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
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rxdmacfg.b_DMA2D = 0; /* N/A */
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rxdmacfg.b_RESTART= 0; /* N/A */
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rxdmacfg.b_DI_SEL = 0; /* N/A */
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rxdmacfg.b_DI_EN = 0; /* no interrupt */
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rxdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
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rxdmacfg.b_FLOW = 7; /* large desc flow */
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#endif
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const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 };
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#if 0
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txdmacfg.b_DMA_EN = 1; /* enabled */
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txdmacfg.b_WNR = 0; /* read from memory */
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txdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
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txdmacfg.b_DMA2D = 0; /* N/A */
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txdmacfg.b_RESTART= 0; /* N/A */
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txdmacfg.b_DI_SEL = 0; /* N/A */
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txdmacfg.b_DI_EN = 0; /* no interrupt */
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txdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
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txdmacfg.b_FLOW = 7; /* large desc flow */
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#endif
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ADI_ETHER_BUFFER *SetupRxBuffer(int no);
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ADI_ETHER_BUFFER *SetupTxBuffer(int no);
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static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd);
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static void bfin_EMAC_halt(struct eth_device *dev);
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static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
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int length);
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static int bfin_EMAC_recv(struct eth_device *dev);
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int bfin_EMAC_initialize(bd_t * bis)
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{
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struct eth_device *dev;
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dev = (struct eth_device *)malloc(sizeof(*dev));
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if (dev == NULL)
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hang();
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memset(dev, 0, sizeof(*dev));
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sprintf(dev->name, "BF537 ETHERNET");
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dev->iobase = 0;
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dev->priv = 0;
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dev->init = bfin_EMAC_init;
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dev->halt = bfin_EMAC_halt;
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dev->send = bfin_EMAC_send;
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dev->recv = bfin_EMAC_recv;
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eth_register(dev);
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return 1;
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}
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static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
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int length)
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{
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int i;
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int result = 0;
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unsigned int *buf;
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buf = (unsigned int *)packet;
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if (length <= 0) {
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printf("Ethernet: bad packet size: %d\n", length);
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goto out;
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}
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if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
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printf("Ethernet: tx DMA error\n");
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goto out;
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}
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for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
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if (i > TOUT_LOOP) {
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puts("Ethernet: tx time out\n");
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goto out;
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}
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}
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txbuf[txIdx]->FrmData->NoBytes = length;
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memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
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txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
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*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
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*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
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*pEMAC_OPMODE |= TE;
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for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
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if (i > TOUT_LOOP) {
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puts("Ethernet: tx error\n");
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goto out;
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}
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}
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result = txbuf[txIdx]->StatusWord;
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txbuf[txIdx]->StatusWord = 0;
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if ((txIdx + 1) >= TX_BUF_CNT)
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txIdx = 0;
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else
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txIdx++;
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out:
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DEBUGF("BFIN EMAC send: length = %d\n", length);
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return result;
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}
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static int bfin_EMAC_recv(struct eth_device *dev)
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{
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int length = 0;
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for (;;) {
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if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
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length = -1;
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break;
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}
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if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
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printf("Ethernet: rx dma overrun\n");
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break;
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}
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if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
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printf("Ethernet: rx error\n");
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break;
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}
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length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
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if (length <= 4) {
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printf("Ethernet: bad frame\n");
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break;
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}
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NetRxPackets[rxIdx] =
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(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
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NetReceive(NetRxPackets[rxIdx], length - 4);
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*pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
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rxbuf[rxIdx]->StatusWord = 0x00000000;
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if ((rxIdx + 1) >= PKTBUFSRX)
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rxIdx = 0;
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else
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rxIdx++;
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}
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return length;
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}
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/**************************************************************
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*
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* Ethernet Initialization Routine
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*
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*************************************************************/
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static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd)
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{
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u32 opmode;
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int dat;
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int i;
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DEBUGF("Eth_init: ......\n");
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txIdx = 0;
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rxIdx = 0;
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/* Initialize System Register */
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if (SetupSystemRegs(&dat) < 0)
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return -1;
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/* Initialize EMAC address */
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SetupMacAddr(SrcAddr);
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/* Initialize TX and RX buffer */
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for (i = 0; i < PKTBUFSRX; i++) {
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rxbuf[i] = SetupRxBuffer(i);
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if (i > 0) {
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rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
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&(rxbuf[i]->Dma[0]);
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if (i == (PKTBUFSRX - 1))
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rxbuf[i]->Dma[1].NEXT_DESC_PTR =
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&(rxbuf[0]->Dma[0]);
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}
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}
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for (i = 0; i < TX_BUF_CNT; i++) {
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txbuf[i] = SetupTxBuffer(i);
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if (i > 0) {
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txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
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&(txbuf[i]->Dma[0]);
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if (i == (TX_BUF_CNT - 1))
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txbuf[i]->Dma[1].NEXT_DESC_PTR =
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&(txbuf[0]->Dma[0]);
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}
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}
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/* Set RX DMA */
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*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
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*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
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/* Wait MII done */
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PollMdcDone();
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/* We enable only RX here */
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/* ASTP : Enable Automatic Pad Stripping
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PR : Promiscuous Mode for test
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PSF : Receive frames with total length less than 64 bytes.
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FDMODE : Full Duplex Mode
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LB : Internal Loopback for test
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RE : Receiver Enable */
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if (dat == FDMODE)
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opmode = ASTP | FDMODE | PSF;
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else
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opmode = ASTP | PSF;
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opmode |= RE;
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#ifdef CONFIG_BFIN_MAC_RMII
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opmode |= TE | RMII;
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#endif
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/* Turn on the EMAC */
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*pEMAC_OPMODE = opmode;
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return 0;
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}
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static void bfin_EMAC_halt(struct eth_device *dev)
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{
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DEBUGF("Eth_halt: ......\n");
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/* Turn off the EMAC */
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*pEMAC_OPMODE = 0x00000000;
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/* Turn off the EMAC RX DMA */
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*pDMA1_CONFIG = 0x0000;
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*pDMA2_CONFIG = 0x0000;
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}
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void SetupMacAddr(u8 * MACaddr)
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{
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char *tmp, *end;
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int i;
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/* this depends on a little-endian machine */
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tmp = getenv("ethaddr");
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if (tmp) {
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for (i = 0; i < 6; i++) {
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MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
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if (tmp)
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tmp = (*end) ? end + 1 : end;
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}
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#ifndef CONFIG_NETCONSOLE
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printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n",
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MACaddr[0], MACaddr[1],
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MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]);
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#endif
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*pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 |
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MACaddr[2] << 16 | MACaddr[3] << 24;
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*pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8;
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}
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}
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void PollMdcDone(void)
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{
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/* poll the STABUSY bit */
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while (*pEMAC_STAADD & STABUSY) ;
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}
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void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
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{
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PollMdcDone();
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*pEMAC_STADAT = Data;
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*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
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STAOP | STAIE | STABUSY;
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}
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/*********************************************************************************
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* Read an off-chip register in a PHY through the MDC/MDIO port *
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*********************************************************************************/
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u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
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{
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u16 Data;
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PollMdcDone();
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*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
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STAIE | STABUSY;
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PollMdcDone();
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Data = (u16) * pEMAC_STADAT;
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PHYregs[RegAddr] = Data; /* save shadow copy */
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return Data;
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}
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void SoftResetPHY(void)
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{
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u16 phydat;
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/* set the reset bit */
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WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
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/* and clear it again */
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WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
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do {
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/* poll until reset is complete */
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phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
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} while ((phydat & PHY_RESET) != 0);
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}
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int SetupSystemRegs(int *opmode)
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{
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u16 sysctl, phydat;
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int count = 0;
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/* Enable PHY output */
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*pVR_CTL |= PHYCLKOE;
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/* MDC = 2.5 MHz */
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sysctl = SET_MDCDIV(24);
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/* Odd word alignment for Receive Frame DMA word */
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/* Configure checksum support and rcve frame word alignment */
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sysctl |= RXDWA | RXCKS;
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*pEMAC_SYSCTL = sysctl;
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/* auto negotiation on */
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/* full duplex */
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/* 100 Mbps */
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phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
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WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
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do {
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udelay(1000);
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phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
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if (count > 3000) {
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printf
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("Link is down, please check your network connection\n");
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return -1;
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}
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count++;
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} while (!(phydat & 0x0004));
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phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
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if ((phydat & 0x0100) || (phydat & 0x0040))
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*opmode = FDMODE;
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else
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*opmode = 0;
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*pEMAC_MMC_CTL = RSTC | CROLL;
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/* Initialize the TX DMA channel registers */
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*pDMA2_X_COUNT = 0;
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*pDMA2_X_MODIFY = 4;
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*pDMA2_Y_COUNT = 0;
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*pDMA2_Y_MODIFY = 0;
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/* Initialize the RX DMA channel registers */
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*pDMA1_X_COUNT = 0;
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*pDMA1_X_MODIFY = 4;
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*pDMA1_Y_COUNT = 0;
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*pDMA1_Y_MODIFY = 0;
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return 0;
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}
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ADI_ETHER_BUFFER *SetupRxBuffer(int no)
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{
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ADI_ETHER_FRAME_BUFFER *frmbuf;
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ADI_ETHER_BUFFER *buf;
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int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
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int total_size = nobytes_buffer + RECV_BUFSIZE;
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buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
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frmbuf =
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(ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
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nobytes_buffer);
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memset(buf, 0x00, nobytes_buffer);
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buf->FrmData = frmbuf;
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memset(frmbuf, 0xfe, RECV_BUFSIZE);
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/* set up first desc to point to receive frame buffer */
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buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
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buf->Dma[0].START_ADDR = (u32) buf->FrmData;
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buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
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buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
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buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
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buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
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/* set up second desc to point to status word */
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buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
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buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
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buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
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buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
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buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
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buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
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buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
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return buf;
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}
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ADI_ETHER_BUFFER *SetupTxBuffer(int no)
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{
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ADI_ETHER_FRAME_BUFFER *frmbuf;
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ADI_ETHER_BUFFER *buf;
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int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
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int total_size = nobytes_buffer + RECV_BUFSIZE;
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buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
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frmbuf =
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(ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
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nobytes_buffer);
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memset(buf, 0x00, nobytes_buffer);
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buf->FrmData = frmbuf;
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memset(frmbuf, 0x00, RECV_BUFSIZE);
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/* set up first desc to point to receive frame buffer */
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buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
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buf->Dma[0].START_ADDR = (u32) buf->FrmData;
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buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
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buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
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buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
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buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
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/* set up second desc to point to status word */
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buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
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buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
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buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
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buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
|
|
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
|
|
buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
|
|
buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
|
|
|
|
return buf;
|
|
}
|
|
|
|
#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
|
|
int ether_post_test(int flags)
|
|
{
|
|
uchar buf[64];
|
|
int i, value = 0;
|
|
int length;
|
|
|
|
printf("\n--------");
|
|
bfin_EMAC_init(NULL, NULL);
|
|
/* construct the package */
|
|
buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
|
|
buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
|
|
buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
|
|
buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
|
|
buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
|
|
buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
|
|
buf[12] = 0x08; /* Type: ARP */
|
|
buf[13] = 0x06;
|
|
buf[14] = 0x00; /* Hardware type: Ethernet */
|
|
buf[15] = 0x01;
|
|
buf[16] = 0x08; /* Protocal type: IP */
|
|
buf[17] = 0x00;
|
|
buf[18] = 0x06; /* Hardware size */
|
|
buf[19] = 0x04; /* Protocol size */
|
|
buf[20] = 0x00; /* Opcode: request */
|
|
buf[21] = 0x01;
|
|
|
|
for (i = 0; i < 42; i++)
|
|
buf[i + 22] = i;
|
|
printf("--------Send 64 bytes......\n");
|
|
bfin_EMAC_send(NULL, (volatile void *)buf, 64);
|
|
for (i = 0; i < 100; i++) {
|
|
udelay(10000);
|
|
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
|
|
value = 1;
|
|
break;
|
|
}
|
|
}
|
|
if (value == 0) {
|
|
printf("--------EMAC can't receive any data\n");
|
|
eth_halt();
|
|
return -1;
|
|
}
|
|
length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
|
|
for (i = 0; i < length; i++) {
|
|
if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
|
|
printf("--------EMAC receive error data!\n");
|
|
eth_halt();
|
|
return -1;
|
|
}
|
|
}
|
|
printf("--------receive %d bytes, matched\n", length);
|
|
bfin_EMAC_halt(NULL);
|
|
return 0;
|
|
}
|
|
#endif
|
|
#endif
|
|
|