upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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512 lines
14 KiB
512 lines
14 KiB
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2005-2007
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* Modified for InterControl digsyMTC MPC5200 board by
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* Frank Bodammer, GCD Hard- & Software GmbH,
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* frank.bodammer@gcd-solutions.de
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*
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* (C) Copyright 2009 Semihalf
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* Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software\; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation\; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY\; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program\; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
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#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
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/*
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* Valid values for CONFIG_SYS_TEXT_BASE are:
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* 0xFFF00000 boot high (standard configuration)
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* 0xFE000000 boot low
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* 0x00100000 boot from RAM (for testing only)
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*/
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
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#endif
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCI_BOOTDELAY 250
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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/*
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* Partitions
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*/
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#define CONFIG_DOS_PARTITION
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#define CONFIG_BZIP2
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/*
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* Video
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*/
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#define CONFIG_VIDEO
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_MB862xx
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#define CONFIG_VIDEO_MB862xx_ACCEL
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#define CONFIG_VIDEO_CORALP
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_VIDEO_BMP_GZIP
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
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/* Coral-PA clock frequency, geo and other both 133MHz */
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#define CONFIG_SYS_MB862xx_CCF 0x00050000
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/* Video SDRAM parameters */
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#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
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#endif
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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#define CONFIG_CMD_DFL
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_USB
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#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
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#define CONFIG_SYS_LOWBOOT 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 1
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fw_image=digsyMPC.img\0" \
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"mtcb_start=mtc led diag orange; run mtcb_1\0" \
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"mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
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"do mtc led $x; done\0" \
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"mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
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"else run mtcb_fw; fi\0" \
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"mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
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"else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
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"mtcb_update=mtc led user1 orange;" \
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"while mtc key; do ; done; run mtcb_2;\0" \
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"mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
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"mtcb_usb1=if fatload usb 0 400000 script.img; " \
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"then run mtcb_doscript; else run mtcb_usb2; fi\0" \
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"mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
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"then run mtcb_dousb; else run mtcb_ide; fi\0" \
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"mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
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"run mtcb_wait_flickr mtcb_ds_1;\0" \
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"mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
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"source 400000; else run mtcb_error; fi\0" \
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"mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
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"mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
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"else run mtcb_error; fi\0" \
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"mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
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"run mtcb_checkfw\0" \
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"mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
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"else run mtcb_error; fi\0" \
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"mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
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"mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
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"mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
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"mtcb_uledflckr=mtc led user1 orange 11\0" \
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"mtcb_error=mtc led user1 red\0" \
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"mtcb_clear=erase ff000000 ff0fffff\0" \
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"mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
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"mtcb_success=mtc led user1 green\0" \
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"mtcb_ide=if fatload ide 0 400000 $fw_image;" \
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"then run mtcb_doide; else run mtcb_error; fi\0" \
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"mtcb_doide=mtc led user2 green 1;" \
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"run mtcb_wait_flickr mtcb_di_1;\0" \
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"mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
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"else run mtcb_error; fi\0" \
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"mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
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"ramdisk_num_sector=16\0" \
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"flash_base=ff000000\0" \
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"flashdisk_size=e00000\0" \
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"env_sector=fff60000\0" \
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"flashdisk_start=ff100000\0" \
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"load_cmd=tftp 400000 digsyMPC.img\0" \
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"clear_cmd=erase ff000000 ff0fffff\0" \
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"flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
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"update_cmd=run load_cmd; " \
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"iminfo 400000; " \
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"run clear_cmd flash_cmd; " \
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"iminfo ff000000\0" \
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"spi_driver=yes\0" \
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"spi_watchdog=no\0" \
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"ftps_start=yes\0" \
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"ftps_user1=admin\0" \
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"ftps_pass1=admin\0" \
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"ftps_base1=/\0" \
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"ftps_home1=/\0" \
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"plc_sio_srv=no\0" \
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"plc_sio_baud=57600\0" \
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"plc_sio_parity=no\0" \
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"plc_sio_stop=1\0" \
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"plc_sio_com=2\0" \
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"plc_eth_srv=yes\0" \
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"plc_eth_port=1200\0" \
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"plc_root=/ide/\0" \
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"diag_level=0\0" \
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"webvisu=no\0" \
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"plc_can1_routing=no\0" \
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"plc_can1_baudrate=250\0" \
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"plc_can2_routing=no\0" \
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"plc_can2_baudrate=250\0" \
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"plc_can3_routing=no\0" \
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"plc_can3_baudrate=250\0" \
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"plc_can4_routing=no\0" \
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"plc_can4_baudrate=250\0" \
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"netdev=eth0\0" \
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"console=ttyPSC0\0" \
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"kernel_addr_r=400000\0" \
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"fdt_addr_r=600000\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:${hostname}:${netdev}:off panic=1\0" \
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"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
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"tftp ${fdt_addr_r} ${fdt_file};" \
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"run nfsargs addip addcons;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"load=tftp 200000 ${u-boot}\0" \
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"update=protect off FFF00000 +${filesize};" \
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"erase FFF00000 +${filesize};" \
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"cp.b 200000 FFF00000 ${filesize};" \
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"protect on FFF00000 +${filesize}\0" \
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""
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#define CONFIG_BOOTCOMMAND "run mtcb_start"
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/*
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* SPI configuration
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*/
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#define CONFIG_HARD_SPI 1
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#define CONFIG_MPC52XX_SPI 1
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_MODULE 1
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
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/*
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* RTC configuration
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*/
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#if defined(CONFIG_DIGSY_REV5)
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#define CONFIG_SYS_I2C_RTC_ADDR 0x56
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#define CONFIG_RTC_RV3029
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/* Enable 5k Ohm trickle charge resistor */
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#define CONFIG_SYS_RV3029_TCR 0x20
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#else
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
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#endif
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#if defined(CONFIG_DIGSY_REV5)
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE_CS1}
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#define CONFIG_SYS_UPDATE_FLASH_SIZE
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#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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#else
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#endif
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_FLASH_16BIT
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_SIZE 0x01000000
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_CPU "PowerPC,5200@0"
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#define OF_SOC "soc5200@f0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_MISC_INIT_R
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#if defined(CONFIG_LOWBOOT)
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#define CONFIG_ENV_ADDR 0xFF060000
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#else /* CONFIG_LOWBOOT */
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#define CONFIG_ENV_ADDR 0xFFF60000
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#endif /* CONFIG_LOWBOOT */
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#if !defined(CONFIG_SYS_LOWBOOT)
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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#else
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#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
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#endif
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/*
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* Use SRAM until RAM will be available
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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#if defined(CONFIG_DIGSY_REV5)
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#define CONFIG_PHY_ADDR 0x01
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#else
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#define CONFIG_PHY_ADDR 0x00
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#endif
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#define CONFIG_PHY_RESET_DELAY 1000
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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/*
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* GPIO configuration
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* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
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* Bit 0 (mask 0x80000000) : 0x1
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* SPI on Tmr2/3/4/5 pins
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* Bit 2:3 (mask 0x30000000) : 0x2
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* ATA cs0/1 on csb_4/5
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* Bit 6:7 (mask 0x03000000) : 0x2
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* Ethernet 100Mbit with MD
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* Bits 12:15 (mask 0x000f0000): 0x5
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* USB - Two UARTs
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* Bits 18:19 (mask 0x00003000) : 0x2
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* PSC3 - USB2 on PSC3
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* Bits 20:23 (mask 0x00000f00) : 0x1
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* PSC2 - CAN1&2 on PSC2 pins
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* Bits 25:27 (mask 0x00000070) : 0x1
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* PSC1 - AC97 functionality
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* Bits 29:31 (mask 0x00000007) : 0x2
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_AUTO_COMPLETE 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR " "
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#define CONFIG_LOOPW 1
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#define CONFIG_MX_CYCLIC 1
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 32
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_ALT_MEMTEST
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#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
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#define CONFIG_SYS_MEMTEST_START 0x00010000
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#define CONFIG_SYS_MEMTEST_END 0x019fffff
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_SYS_HZ 1000
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_SDRAM_CS1 1
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#define CONFIG_SYS_XLB_PIPELINING 1
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#if defined(CONFIG_SYS_LOWBOOT)
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
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#endif
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#define CONFIG_SYS_CS4_START 0x60000000
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#define CONFIG_SYS_CS4_SIZE 0x1000
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#define CONFIG_SYS_CS4_CFG 0x0008FC00
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS0_CFG 0x0002DD00
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#if defined(CONFIG_DIGSY_REV5)
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#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
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#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS1_CFG 0x0002DD00
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#endif
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
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#if !defined(CONFIG_SYS_LOWBOOT)
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#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
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#else
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#define CONFIG_SYS_RESET_ADDRESS 0xff000100
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#endif
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/*
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* USB
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*/
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_OHCI_BE_CONTROLLER
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_CLOCK 0x00013333
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#define CONFIG_USB_CONFIG 0x00002000
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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/*
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* IDE/ATA
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*/
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#define CONFIG_IDE_RESET
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_ATA_CS_ON_I2C2
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_IDE_MAXDEVICE 1
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
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#define CONFIG_SYS_ATA_STRIDE 4
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#define CONFIG_ATAPI 1
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#define CONFIG_LBA48 1
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#endif /* __CONFIG_H */
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