upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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619 lines
18 KiB
619 lines
18 KiB
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <command.h>
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#include <net.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/fec.h>
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#include <asm/immap.h>
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#undef ET_DEBUG
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#undef MII_DEBUG
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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#define PKT_MAXBUF_SIZE 1518
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#define PKT_MINBUF_SIZE 64
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#define PKT_MAXBLR_SIZE 1520
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#define LAST_PKTBUFSRX PKTBUFSRX - 1
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#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
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#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
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DECLARE_GLOBAL_DATA_PTR;
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struct fec_info_s fec_info[] = {
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#ifdef CONFIG_SYS_FEC0_IOBASE
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{
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0, /* index */
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CONFIG_SYS_FEC0_IOBASE, /* io base */
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CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
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CONFIG_SYS_FEC0_MIIBASE, /* mii base */
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-1, /* phy_addr */
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0, /* duplex and speed */
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0, /* phy name */
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0, /* phyname init */
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0, /* RX BD */
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0, /* TX BD */
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0, /* rx Index */
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0, /* tx Index */
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0, /* tx buffer */
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0, /* initialized flag */
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(struct fec_info_s *)-1,
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},
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#endif
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#ifdef CONFIG_SYS_FEC1_IOBASE
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{
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1, /* index */
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CONFIG_SYS_FEC1_IOBASE, /* io base */
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CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
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CONFIG_SYS_FEC1_MIIBASE, /* mii base */
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-1, /* phy_addr */
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0, /* duplex and speed */
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0, /* phy name */
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0, /* phy name init */
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#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
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(cbd_t *)DBUF_LENGTH, /* RX BD */
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#else
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0, /* RX BD */
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#endif
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0, /* TX BD */
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0, /* rx Index */
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0, /* tx Index */
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0, /* tx buffer */
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0, /* initialized flag */
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(struct fec_info_s *)-1,
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}
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#endif
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};
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int fec_recv(struct eth_device *dev);
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int fec_init(struct eth_device *dev, bd_t * bd);
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void fec_halt(struct eth_device *dev);
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void fec_reset(struct eth_device *dev);
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void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
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{
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if ((dup_spd >> 16) == FULL) {
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/* Set maximum frame length */
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fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
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FEC_RCR_PROM | 0x100;
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fecp->tcr = FEC_TCR_FDEN;
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} else {
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/* Half duplex mode */
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fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
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FEC_RCR_MII_MODE | FEC_RCR_DRT;
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fecp->tcr &= ~FEC_TCR_FDEN;
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}
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if ((dup_spd & 0xFFFF) == _100BASET) {
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#ifdef CONFIG_MCF5445x
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fecp->rcr &= ~0x200; /* disabled 10T base */
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#endif
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#ifdef MII_DEBUG
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printf("100Mbps\n");
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#endif
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bd->bi_ethspeed = 100;
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} else {
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#ifdef CONFIG_MCF5445x
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fecp->rcr |= 0x200; /* enabled 10T base */
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#endif
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#ifdef MII_DEBUG
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printf("10Mbps\n");
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#endif
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bd->bi_ethspeed = 10;
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}
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}
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static int fec_send(struct eth_device *dev, void *packet, int length)
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{
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struct fec_info_s *info = dev->priv;
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volatile fec_t *fecp = (fec_t *) (info->iobase);
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int j, rc;
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u16 phyStatus;
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miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
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/* section 16.9.23.3
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* Wait for ready
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*/
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j = 0;
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while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
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(j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("TX not ready\n");
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}
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info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
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info->txbd[info->txIdx].cbd_datlen = length;
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info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
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/* Activate transmit Buffer Descriptor polling */
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fecp->tdar = 0x01000000; /* Descriptor polling active */
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#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
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/*
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* FEC unable to initial transmit data packet.
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* A nop will ensure the descriptor polling active completed.
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* CF Internal RAM has shorter cycle access than DRAM. If use
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* DRAM as Buffer descriptor and data, a nop is a must.
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* Affect only V2 and V3.
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*/
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__asm__ ("nop");
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#endif
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#ifdef CONFIG_SYS_UNIFY_CACHE
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icache_invalid();
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#endif
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j = 0;
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while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
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(j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("TX timeout\n");
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}
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#ifdef ET_DEBUG
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printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
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__FILE__, __LINE__, __FUNCTION__, j,
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info->txbd[info->txIdx].cbd_sc,
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(info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
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#endif
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/* return only status bits */
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rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
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info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
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return rc;
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}
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int fec_recv(struct eth_device *dev)
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{
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struct fec_info_s *info = dev->priv;
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volatile fec_t *fecp = (fec_t *) (info->iobase);
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int length;
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for (;;) {
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#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
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#endif
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#ifdef CONFIG_SYS_UNIFY_CACHE
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icache_invalid();
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#endif
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/* section 16.9.23.2 */
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if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
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length = -1;
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break; /* nothing received - leave for() loop */
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}
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length = info->rxbd[info->rxIdx].cbd_datlen;
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if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
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printf("%s[%d] err: %x\n",
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__FUNCTION__, __LINE__,
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info->rxbd[info->rxIdx].cbd_sc);
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#ifdef ET_DEBUG
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printf("%s[%d] err: %x\n",
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__FUNCTION__, __LINE__,
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info->rxbd[info->rxIdx].cbd_sc);
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#endif
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} else {
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length -= 4;
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/* Pass the packet up to the protocol layers. */
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net_process_received_packet(net_rx_packets[info->rxIdx],
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length);
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fecp->eir |= FEC_EIR_RXF;
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}
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/* Give the buffer back to the FEC. */
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info->rxbd[info->rxIdx].cbd_datlen = 0;
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/* wrap around buffer index when necessary */
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if (info->rxIdx == LAST_PKTBUFSRX) {
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info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
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info->rxIdx = 0;
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} else {
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info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
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info->rxIdx++;
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}
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/* Try to fill Buffer Descriptors */
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fecp->rdar = 0x01000000; /* Descriptor polling active */
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}
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return length;
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}
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#ifdef ET_DEBUG
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void dbgFecRegs(struct eth_device *dev)
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{
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struct fec_info_s *info = dev->priv;
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volatile fec_t *fecp = (fec_t *) (info->iobase);
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printf("=====\n");
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printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
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printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
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printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
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printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
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printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
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printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
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printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
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printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
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printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
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printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
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printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
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printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
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printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
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printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
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printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
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printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
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printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
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printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
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printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
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printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
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printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
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printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
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printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
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printf("\n");
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printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
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fecp->rmon_t_drop);
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printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
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fecp->rmon_t_packets);
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printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
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fecp->rmon_t_bc_pkt);
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printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
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fecp->rmon_t_mc_pkt);
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printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
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fecp->rmon_t_crc_align);
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printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
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fecp->rmon_t_undersize);
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printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
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fecp->rmon_t_oversize);
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printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
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fecp->rmon_t_frag);
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printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
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fecp->rmon_t_jab);
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printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
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fecp->rmon_t_col);
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printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
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fecp->rmon_t_p64);
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printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
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fecp->rmon_t_p65to127);
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printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
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fecp->rmon_t_p128to255);
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printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
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fecp->rmon_t_p256to511);
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printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
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fecp->rmon_t_p512to1023);
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printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
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fecp->rmon_t_p1024to2047);
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printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
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fecp->rmon_t_p_gte2048);
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printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
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fecp->rmon_t_octets);
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printf("\n");
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printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
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fecp->ieee_t_drop);
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printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
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fecp->ieee_t_frame_ok);
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printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
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fecp->ieee_t_1col);
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printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
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fecp->ieee_t_mcol);
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printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
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fecp->ieee_t_def);
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printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
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fecp->ieee_t_lcol);
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printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
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fecp->ieee_t_excol);
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printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
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fecp->ieee_t_macerr);
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printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
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fecp->ieee_t_cserr);
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printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
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fecp->ieee_t_sqe);
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printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
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fecp->ieee_t_fdxfc);
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printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
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fecp->ieee_t_octets_ok);
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printf("\n");
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printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
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fecp->rmon_r_drop);
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printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
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fecp->rmon_r_packets);
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printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
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fecp->rmon_r_bc_pkt);
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printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
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fecp->rmon_r_mc_pkt);
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printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
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fecp->rmon_r_crc_align);
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printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
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fecp->rmon_r_undersize);
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printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
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fecp->rmon_r_oversize);
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printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
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fecp->rmon_r_frag);
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printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
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fecp->rmon_r_jab);
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printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
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fecp->rmon_r_p64);
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printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
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fecp->rmon_r_p65to127);
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printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
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fecp->rmon_r_p128to255);
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printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
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fecp->rmon_r_p256to511);
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printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
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fecp->rmon_r_p512to1023);
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printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
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fecp->rmon_r_p1024to2047);
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printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
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fecp->rmon_r_p_gte2048);
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printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
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fecp->rmon_r_octets);
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printf("\n");
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printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
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fecp->ieee_r_drop);
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printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
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fecp->ieee_r_frame_ok);
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printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
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|
fecp->ieee_r_crc);
|
|
printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
|
|
fecp->ieee_r_align);
|
|
printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
|
|
fecp->ieee_r_macerr);
|
|
printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
|
|
fecp->ieee_r_fdxfc);
|
|
printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
|
|
fecp->ieee_r_octets_ok);
|
|
|
|
printf("\n\n\n");
|
|
}
|
|
#endif
|
|
|
|
int fec_init(struct eth_device *dev, bd_t * bd)
|
|
{
|
|
struct fec_info_s *info = dev->priv;
|
|
volatile fec_t *fecp = (fec_t *) (info->iobase);
|
|
int i;
|
|
uchar ea[6];
|
|
|
|
fecpin_setclear(dev, 1);
|
|
|
|
fec_reset(dev);
|
|
|
|
#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
|
|
defined (CONFIG_SYS_DISCOVER_PHY)
|
|
|
|
mii_init();
|
|
|
|
setFecDuplexSpeed(fecp, bd, info->dup_spd);
|
|
#else
|
|
#ifndef CONFIG_SYS_DISCOVER_PHY
|
|
setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
|
|
#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
|
|
#endif /* CONFIG_CMD_MII || CONFIG_MII */
|
|
|
|
/* We use strictly polling mode only */
|
|
fecp->eimr = 0;
|
|
|
|
/* Clear any pending interrupt */
|
|
fecp->eir = 0xffffffff;
|
|
|
|
/* Set station address */
|
|
if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
|
|
#ifdef CONFIG_SYS_FEC1_IOBASE
|
|
volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
|
|
eth_env_get_enetaddr("eth1addr", ea);
|
|
fecp1->palr =
|
|
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
|
|
fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
|
|
#endif
|
|
eth_env_get_enetaddr("ethaddr", ea);
|
|
fecp->palr =
|
|
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
|
|
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
|
|
} else {
|
|
#ifdef CONFIG_SYS_FEC0_IOBASE
|
|
volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
|
|
eth_env_get_enetaddr("ethaddr", ea);
|
|
fecp0->palr =
|
|
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
|
|
fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
|
|
#endif
|
|
#ifdef CONFIG_SYS_FEC1_IOBASE
|
|
eth_env_get_enetaddr("eth1addr", ea);
|
|
fecp->palr =
|
|
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
|
|
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
|
|
#endif
|
|
}
|
|
|
|
/* Clear unicast address hash table */
|
|
fecp->iaur = 0;
|
|
fecp->ialr = 0;
|
|
|
|
/* Clear multicast address hash table */
|
|
fecp->gaur = 0;
|
|
fecp->galr = 0;
|
|
|
|
/* Set maximum receive buffer size. */
|
|
fecp->emrbr = PKT_MAXBLR_SIZE;
|
|
|
|
/*
|
|
* Setup Buffers and Buffer Desriptors
|
|
*/
|
|
info->rxIdx = 0;
|
|
info->txIdx = 0;
|
|
|
|
/*
|
|
* Setup Receiver Buffer Descriptors (13.14.24.18)
|
|
* Settings:
|
|
* Empty, Wrap
|
|
*/
|
|
for (i = 0; i < PKTBUFSRX; i++) {
|
|
info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
|
|
info->rxbd[i].cbd_datlen = 0; /* Reset */
|
|
info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
|
|
}
|
|
info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
|
|
|
|
/*
|
|
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
|
|
* Settings:
|
|
* Last, Tx CRC
|
|
*/
|
|
for (i = 0; i < TX_BUF_CNT; i++) {
|
|
info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
|
|
info->txbd[i].cbd_datlen = 0; /* Reset */
|
|
info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
|
|
}
|
|
info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
|
|
|
|
/* Set receive and transmit descriptor base */
|
|
fecp->erdsr = (unsigned int)(&info->rxbd[0]);
|
|
fecp->etdsr = (unsigned int)(&info->txbd[0]);
|
|
|
|
/* Now enable the transmit and receive processing */
|
|
fecp->ecr |= FEC_ECR_ETHER_EN;
|
|
|
|
/* And last, try to fill Rx Buffer Descriptors */
|
|
fecp->rdar = 0x01000000; /* Descriptor polling active */
|
|
|
|
return 1;
|
|
}
|
|
|
|
void fec_reset(struct eth_device *dev)
|
|
{
|
|
struct fec_info_s *info = dev->priv;
|
|
volatile fec_t *fecp = (fec_t *) (info->iobase);
|
|
int i;
|
|
|
|
fecp->ecr = FEC_ECR_RESET;
|
|
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
|
udelay(1);
|
|
}
|
|
if (i == FEC_RESET_DELAY) {
|
|
printf("FEC_RESET_DELAY timeout\n");
|
|
}
|
|
}
|
|
|
|
void fec_halt(struct eth_device *dev)
|
|
{
|
|
struct fec_info_s *info = dev->priv;
|
|
|
|
fec_reset(dev);
|
|
|
|
fecpin_setclear(dev, 0);
|
|
|
|
info->rxIdx = info->txIdx = 0;
|
|
memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
|
|
memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
|
|
memset(info->txbuf, 0, DBUF_LENGTH);
|
|
}
|
|
|
|
int mcffec_initialize(bd_t * bis)
|
|
{
|
|
struct eth_device *dev;
|
|
int i;
|
|
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
|
|
u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
|
|
#endif
|
|
|
|
for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
|
|
|
|
dev =
|
|
(struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
|
|
sizeof *dev);
|
|
if (dev == NULL)
|
|
hang();
|
|
|
|
memset(dev, 0, sizeof(*dev));
|
|
|
|
sprintf(dev->name, "FEC%d", fec_info[i].index);
|
|
|
|
dev->priv = &fec_info[i];
|
|
dev->init = fec_init;
|
|
dev->halt = fec_halt;
|
|
dev->send = fec_send;
|
|
dev->recv = fec_recv;
|
|
|
|
/* setup Receive and Transmit buffer descriptor */
|
|
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
|
|
fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
|
|
tmp = (u32)fec_info[i].rxbd;
|
|
fec_info[i].txbd =
|
|
(cbd_t *)((u32)fec_info[i].txbd + tmp +
|
|
(PKTBUFSRX * sizeof(cbd_t)));
|
|
tmp = (u32)fec_info[i].txbd;
|
|
fec_info[i].txbuf =
|
|
(char *)((u32)fec_info[i].txbuf + tmp +
|
|
(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
|
|
tmp = (u32)fec_info[i].txbuf;
|
|
#else
|
|
fec_info[i].rxbd =
|
|
(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
|
|
(PKTBUFSRX * sizeof(cbd_t)));
|
|
fec_info[i].txbd =
|
|
(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
|
|
(TX_BUF_CNT * sizeof(cbd_t)));
|
|
fec_info[i].txbuf =
|
|
(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
|
|
#endif
|
|
|
|
#ifdef ET_DEBUG
|
|
printf("rxbd %x txbd %x\n",
|
|
(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
|
|
#endif
|
|
|
|
fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
|
|
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
int retval;
|
|
struct mii_dev *mdiodev = mdio_alloc();
|
|
if (!mdiodev)
|
|
return -ENOMEM;
|
|
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
|
|
mdiodev->read = mcffec_miiphy_read;
|
|
mdiodev->write = mcffec_miiphy_write;
|
|
|
|
retval = mdio_register(mdiodev);
|
|
if (retval < 0)
|
|
return retval;
|
|
#endif
|
|
if (i > 0)
|
|
fec_info[i - 1].next = &fec_info[i];
|
|
}
|
|
fec_info[i - 1].next = &fec_info[0];
|
|
|
|
/* default speed */
|
|
bis->bi_ethspeed = 10;
|
|
|
|
return 0;
|
|
}
|
|
|