upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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111 lines
2.8 KiB
111 lines
2.8 KiB
/*
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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*
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* Based on U-Boot and RedBoot sources for several different i.mx
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* platforms.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/macro.h>
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#include <asm/arch/macro.h>
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.macro init_clocks
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/*
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* clocks
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*
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* first enable CLKO debug output
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* 0x40000000 enables the debug CLKO signal
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* 0x05000000 sets CLKO divider to 6
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* 0x00600000 makes CLKO parent clk the USB clk
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*/
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write32 0x53f80064, 0x45600000
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/* CCTL: ARM = 399 MHz, AHB = 133 MHz */
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write32 0x53f80008, 0x20034000
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/*
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* PCDR2: NFC = 33.25 MHz
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* This is required for the NAND Flash of this board, which is a Samsung
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* K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
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* the NFC driver in symmetric (i.e. one-cycle) mode.
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*/
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write32 0x53f80020, 0x01010103
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/*
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* enable all implemented clocks in all three
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* clock control registers
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*/
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write32 0x53f8000c, 0x1fffffff
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write32 0x53f80010, 0xffffffff
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write32 0x53f80014, 0xfdfff
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.endm
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.macro init_ddrtype
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/*
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* ddr_type is 3.3v SDRAM
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*/
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write32 0x43fac454, 0x800
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.endm
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/*
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* sdram controller init
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*/
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.macro init_sdram_bank bankaddr, ctl, cfg
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ldr r0, =0xb8001000
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ldr r2, =\bankaddr
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/*
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* reset SDRAM controller
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* then wait for initialization to complete
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*/
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ldr r1, =(1 << 1)
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str r1, [r0, #0x10]
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1: ldr r3, [r0, #0x10]
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tst r3, #(1 << 31)
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beq 1b
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ldr r1, =0x95728
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str r1, [r0, #\cfg] /* config */
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ldr r1, =0x92116480 /* control | precharge */
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str r1, [r0, #\ctl] /* write command to controller */
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str r1, [r2, #0x400] /* command encoded in address */
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ldr r1, =0xa2116480 /* auto refresh */
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str r1, [r0, #\ctl]
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ldrb r3, [r2] /* read dram twice to auto refresh */
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ldrb r3, [r2]
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ldr r1, =0xb2116480 /* control | load mode */
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str r1, [r0, #\ctl] /* write command to controller */
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strb r1, [r2, #0x33] /* command encoded in address */
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ldr r1, =0x82116480 /* control | normal (0)*/
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str r1, [r0, #\ctl] /* write command to controller */
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.endm
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.globl lowlevel_init
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lowlevel_init:
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init_aips
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init_max
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init_m3if
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init_clocks
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init_sdram_bank 0x80000000, 0x0, 0x4
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init_sdram_bank 0x90000000, 0x8, 0xc
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mov pc, lr
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