upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

York Sun 2f78eae506 ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC ... Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>		11 years ago
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arc	…
arm	ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC	11 years ago
avr32	avr32: migrate cache functions	11 years ago
blackfin	…
m68k	m68k: Remove CONFIG_CMD_BEDBUG related code	11 years ago
microblaze	Makefile: Support include files for .dts files	11 years ago
mips	…
nds32	…
nios2	bd_info: remove bi_barudrate member from struct bd_info	11 years ago
openrisc	…
powerpc	…
sandbox	sandbox: change local_irq_save() to macro	11 years ago
sh	…
sparc	…
x86	x86: Enable 32-bit build using x86_64 multilib toolchain	11 years ago
.gitignore	.gitignore: drop include/asm/proc from ignore pattern	11 years ago