upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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382 lines
7.8 KiB
382 lines
7.8 KiB
/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* CPU specific code
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*
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* written or collected and sometimes rewritten by
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* Magnus Damm <damm@bitsmart.com>
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*
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* minor modifications by
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* Wolfgang Denk <wd@denx.de>
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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#include <ppc4xx.h>
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#if !defined(CONFIG_405)
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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#if defined(CONFIG_440)
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#define FREQ_EBC (sys_info.freqEPB)
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#else
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#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
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#endif
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#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
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#define PCI_ASYNC
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int pci_async_enabled(void)
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{
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#if defined(CONFIG_405GP)
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return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
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unsigned long val;
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mfsdr(sdr_sdstp1, val);
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return (val & SDR0_SDSTP1_PAME_MASK);
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#endif
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}
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#endif
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#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
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int pci_arbiter_enabled(void)
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{
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#if defined(CONFIG_405GP)
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return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
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#endif
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#if defined(CONFIG_405EP)
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return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
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#endif
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#if defined(CONFIG_440GP)
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return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
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#endif
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#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
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unsigned long val;
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mfsdr(sdr_sdstp1, val);
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return (val & SDR0_SDSTP1_PAE_MASK);
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#endif
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}
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#endif
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#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440GX) || defined(CONFIG_440SP)
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#define I2C_BOOTROM
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int i2c_bootrom_enabled(void)
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{
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#if defined(CONFIG_405EP)
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return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
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#endif
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#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
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unsigned long val;
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mfsdr(sdr_sdcs, val);
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return (val & SDR0_SDCS_SDD);
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#endif
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}
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#endif
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#if defined(CONFIG_440)
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static int do_chip_reset(unsigned long sys0, unsigned long sys1);
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#endif
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int checkcpu (void)
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{
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#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
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uint pvr = get_pvr();
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ulong clock = gd->cpu_clk;
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char buf[32];
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#if !defined(CONFIG_IOP480)
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sys_info_t sys_info;
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puts ("CPU: ");
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get_sys_info(&sys_info);
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puts("AMCC PowerPC 4");
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
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puts("05");
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#endif
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#if defined(CONFIG_440)
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puts("40");
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#endif
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switch (pvr) {
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case PVR_405GP_RB:
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puts("GP Rev. B");
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break;
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case PVR_405GP_RC:
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puts("GP Rev. C");
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break;
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case PVR_405GP_RD:
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puts("GP Rev. D");
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break;
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#ifdef CONFIG_405GP
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case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
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puts("GP Rev. E");
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break;
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#endif
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case PVR_405CR_RA:
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puts("CR Rev. A");
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break;
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case PVR_405CR_RB:
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puts("CR Rev. B");
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break;
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#ifdef CONFIG_405CR
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case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
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puts("CR Rev. C");
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break;
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#endif
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case PVR_405GPR_RB:
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puts("GPr Rev. B");
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break;
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case PVR_405EP_RB:
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puts("EP Rev. B");
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break;
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#if defined(CONFIG_440)
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case PVR_440GP_RB:
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puts("GP Rev. B");
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/* See errata 1.12: CHIP_4 */
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if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
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(mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
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puts ( "\n\t CPC0_SYSx DCRs corrupted. "
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"Resetting chip ...\n");
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udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
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do_chip_reset ( mfdcr(cpc0_strp0),
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mfdcr(cpc0_strp1) );
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}
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break;
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case PVR_440GP_RC:
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puts("GP Rev. C");
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break;
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case PVR_440GX_RA:
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puts("GX Rev. A");
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break;
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case PVR_440GX_RB:
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puts("GX Rev. B");
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break;
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case PVR_440GX_RC:
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puts("GX Rev. C");
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break;
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case PVR_440GX_RF:
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puts("GX Rev. F");
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break;
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case PVR_440EP_RA:
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puts("EP Rev. A");
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break;
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#ifdef CONFIG_440EP
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case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
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puts("EP Rev. B");
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break;
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case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
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puts("EP Rev. C");
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break;
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#endif /* CONFIG_440EP */
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#ifdef CONFIG_440GR
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case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
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puts("GR Rev. A");
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break;
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case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
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puts("GR Rev. B");
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break;
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#endif /* CONFIG_440GR */
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#endif /* CONFIG_440 */
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case PVR_440SP_RA:
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puts("SP Rev. A");
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break;
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case PVR_440SP_RB:
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puts("SP Rev. B");
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break;
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default:
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printf (" UNKNOWN (PVR=%08x)", pvr);
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break;
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}
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printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
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sys_info.freqPLB / 1000000,
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sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
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FREQ_EBC / 1000000);
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#if defined(I2C_BOOTROM)
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printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
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#endif
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#if defined(CONFIG_PCI)
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printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
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#endif
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#if defined(PCI_ASYNC)
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if (pci_async_enabled()) {
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printf (", PCI async ext clock used");
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} else {
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printf (", PCI sync clock at %lu MHz",
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sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
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}
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#endif
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#if defined(CONFIG_PCI)
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putc('\n');
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#endif
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#if defined(CONFIG_405EP)
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printf (" 16 kB I-Cache 16 kB D-Cache");
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#elif defined(CONFIG_440)
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printf (" 32 kB I-Cache 32 kB D-Cache");
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#else
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printf (" 16 kB I-Cache %d kB D-Cache",
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((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
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#endif
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#endif /* !defined(CONFIG_IOP480) */
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#if defined(CONFIG_IOP480)
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printf ("PLX IOP480 (PVR=%08x)", pvr);
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printf (" at %s MHz:", strmhz(buf, clock));
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printf (" %u kB I-Cache", 4);
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printf (" %u kB D-Cache", 2);
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#endif
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#endif /* !defined(CONFIG_405) */
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
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/*give reset to BCSR*/
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*(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
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#else
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/*
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* Initiate system reset in debug control register DBCR
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*/
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__asm__ __volatile__("lis 3, 0x3000" ::: "r3");
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#if defined(CONFIG_440)
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__asm__ __volatile__("mtspr 0x134, 3");
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#else
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__asm__ __volatile__("mtspr 0x3f2, 3");
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#endif
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#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
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return 1;
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}
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#if defined(CONFIG_440)
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static int do_chip_reset (unsigned long sys0, unsigned long sys1)
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{
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/* Changes to cpc0_sys0 and cpc0_sys1 require chip
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* reset.
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*/
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mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
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mtdcr (cpc0_sys0, sys0);
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mtdcr (cpc0_sys1, sys1);
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mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
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mtspr (dbcr0, 0x20000000); /* Reset the chip */
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return 1;
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}
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#endif
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/*
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* Get timebase clock frequency
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*/
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unsigned long get_tbclk (void)
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{
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#if !defined(CONFIG_IOP480)
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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return (sys_info.freqProcessor);
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#else
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return (66000000);
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#endif
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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int re_enable = disable_interrupts();
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reset_4xx_watchdog();
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if (re_enable) enable_interrupts();
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}
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void
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reset_4xx_watchdog(void)
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{
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/*
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* Clear TSR(WIS) bit
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*/
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mtspr(tsr, 0x40000000);
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}
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#endif /* CONFIG_WATCHDOG */
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