upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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258 lines
6.2 KiB
258 lines
6.2 KiB
/*
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Original Author Guenter Gebhardt
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* Copyright (C) 2006 Micronas GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include "vct.h"
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int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
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{
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u32 enable;
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union dcgu_clk_en1 en1;
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union dcgu_clk_en2 en2;
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switch (setup) {
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case DCGU_SWITCH_ON:
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enable = 1;
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break;
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case DCGU_SWITCH_OFF:
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enable = 0;
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break;
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default:
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printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
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setup);
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return -EINVAL;
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}
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if (module == DCGU_HW_MODULE_CPU)
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en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
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else
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en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
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switch (module) {
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case DCGU_HW_MODULE_MSMC:
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en1.bits.en_clkmsmc = enable;
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break;
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case DCGU_HW_MODULE_SSI_S:
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en1.bits.en_clkssi_s = enable;
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break;
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case DCGU_HW_MODULE_SSI_M:
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en1.bits.en_clkssi_m = enable;
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break;
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case DCGU_HW_MODULE_SMC:
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en1.bits.en_clksmc = enable;
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break;
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case DCGU_HW_MODULE_EBI:
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en1.bits.en_clkebi = enable;
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break;
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case DCGU_HW_MODULE_USB_PLL:
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en1.bits.en_usbpll = enable;
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break;
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case DCGU_HW_MODULE_USB_60:
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en1.bits.en_clkusb60 = enable;
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break;
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case DCGU_HW_MODULE_USB_24:
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en1.bits.en_clkusb24 = enable;
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break;
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case DCGU_HW_MODULE_UART_2:
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en1.bits.en_clkuart2 = enable;
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break;
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case DCGU_HW_MODULE_UART_1:
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en1.bits.en_clkuart1 = enable;
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break;
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case DCGU_HW_MODULE_PERI:
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en1.bits.en_clkperi20 = enable;
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break;
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case DCGU_HW_MODULE_CPU:
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en2.bits.en_clkcpu = enable;
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break;
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case DCGU_HW_MODULE_I2S:
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en1.bits.en_clk_i2s_dly = enable;
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break;
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case DCGU_HW_MODULE_ABP_SCC:
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en1.bits.en_clk_scc_abp = enable;
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break;
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case DCGU_HW_MODULE_SPDIF:
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en1.bits.en_clk_dtv_spdo = enable;
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break;
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case DCGU_HW_MODULE_AD:
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en1.bits.en_clkad = enable;
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break;
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case DCGU_HW_MODULE_MVD:
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en1.bits.en_clkmvd = enable;
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break;
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case DCGU_HW_MODULE_TSD:
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en1.bits.en_clktsd = enable;
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break;
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case DCGU_HW_MODULE_GA:
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en1.bits.en_clkga = enable;
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break;
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case DCGU_HW_MODULE_DVP:
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en1.bits.en_clkdvp = enable;
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break;
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case DCGU_HW_MODULE_MR2:
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en1.bits.en_clkmr2 = enable;
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break;
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case DCGU_HW_MODULE_MR1:
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en1.bits.en_clkmr1 = enable;
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break;
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default:
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printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
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__LINE__, module);
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return -EINVAL;
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}
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/*
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* The reg_read() following the reg_write() below forces the write to
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* be really done on the bus.
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* Otherwise the clock may not be switched on when this API function
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* returns, which may cause an bus error if a registers of the hardware
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* module connected to the clock is accessed.
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*/
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if (module == DCGU_HW_MODULE_CPU) {
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reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
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en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
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} else {
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reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
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en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
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}
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return 0;
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}
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int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
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{
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union dcgu_reset_unit1 val;
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u32 enable;
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switch (setup) {
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case DCGU_SWITCH_ON:
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enable = 1;
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break;
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case DCGU_SWITCH_OFF:
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enable = 0;
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break;
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default:
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printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
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setup);
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return -EINVAL;
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}
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val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
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switch (module) {
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case DCGU_HW_MODULE_MSMC:
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val.bits.swreset_clkmsmc = enable;
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break;
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case DCGU_HW_MODULE_SSI_S:
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val.bits.swreset_clkssi_s = enable;
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break;
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case DCGU_HW_MODULE_SSI_M:
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val.bits.swreset_clkssi_m = enable;
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break;
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case DCGU_HW_MODULE_SMC:
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val.bits.swreset_clksmc = enable;
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break;
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case DCGU_HW_MODULE_EBI:
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val.bits.swreset_clkebi = enable;
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break;
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case DCGU_HW_MODULE_USB_60:
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val.bits.swreset_clkusb60 = enable;
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break;
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case DCGU_HW_MODULE_USB_24:
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val.bits.swreset_clkusb24 = enable;
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break;
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case DCGU_HW_MODULE_UART_2:
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val.bits.swreset_clkuart2 = enable;
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break;
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case DCGU_HW_MODULE_UART_1:
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val.bits.swreset_clkuart1 = enable;
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break;
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case DCGU_HW_MODULE_PWM:
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val.bits.swreset_pwm = enable;
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break;
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case DCGU_HW_MODULE_GPT:
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val.bits.swreset_gpt = enable;
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break;
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case DCGU_HW_MODULE_I2C2:
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val.bits.swreset_i2c2 = enable;
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break;
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case DCGU_HW_MODULE_I2C1:
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val.bits.swreset_i2c1 = enable;
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break;
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case DCGU_HW_MODULE_GPIO2:
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val.bits.swreset_gpio2 = enable;
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break;
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case DCGU_HW_MODULE_GPIO1:
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val.bits.swreset_gpio1 = enable;
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break;
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case DCGU_HW_MODULE_CPU:
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val.bits.swreset_clkcpu = enable;
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break;
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case DCGU_HW_MODULE_I2S:
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val.bits.swreset_clk_i2s_dly = enable;
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break;
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case DCGU_HW_MODULE_ABP_SCC:
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val.bits.swreset_clk_scc_abp = enable;
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break;
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case DCGU_HW_MODULE_SPDIF:
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val.bits.swreset_clk_dtv_spdo = enable;
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break;
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case DCGU_HW_MODULE_AD:
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val.bits.swreset_clkad = enable;
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break;
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case DCGU_HW_MODULE_MVD:
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val.bits.swreset_clkmvd = enable;
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break;
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case DCGU_HW_MODULE_TSD:
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val.bits.swreset_clktsd = enable;
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break;
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case DCGU_HW_MODULE_TSIO:
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val.bits.swreset_clktsio = enable;
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break;
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case DCGU_HW_MODULE_GA:
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val.bits.swreset_clkga = enable;
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break;
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case DCGU_HW_MODULE_MPC:
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val.bits.swreset_clkmpc = enable;
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break;
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case DCGU_HW_MODULE_CVE:
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val.bits.swreset_clkcve = enable;
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break;
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case DCGU_HW_MODULE_DVP:
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val.bits.swreset_clkdvp = enable;
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break;
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case DCGU_HW_MODULE_MR2:
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val.bits.swreset_clkmr2 = enable;
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break;
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case DCGU_HW_MODULE_MR1:
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val.bits.swreset_clkmr1 = enable;
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break;
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default:
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printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
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__LINE__, module);
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return -EINVAL;
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}
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reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
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return 0;
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}
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