upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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113 lines
2.9 KiB
113 lines
2.9 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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void at91_serial0_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
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at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0);
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}
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void at91_serial1_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
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at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1);
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}
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void at91_serial2_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
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at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2);
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}
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void at91_serial3_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
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at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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}
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void at91_serial_hw_init(void)
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{
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#ifdef CONFIG_USART0
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at91_serial0_hw_init();
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#endif
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#ifdef CONFIG_USART1
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at91_serial1_hw_init();
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#endif
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#ifdef CONFIG_USART2
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at91_serial2_hw_init();
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#endif
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#ifdef CONFIG_USART3 /* DBGU */
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at91_serial3_hw_init();
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#endif
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}
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#ifdef CONFIG_HAS_DATAFLASH
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void at91_spi0_hw_init(unsigned long cs_mask)
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{
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at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
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at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
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at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
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if (cs_mask & (1 << 0)) {
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at91_set_A_periph(AT91_PIN_PA28, 1);
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}
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if (cs_mask & (1 << 1)) {
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at91_set_B_periph(AT91_PIN_PB7, 1);
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}
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if (cs_mask & (1 << 2)) {
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at91_set_A_periph(AT91_PIN_PD8, 1);
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}
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if (cs_mask & (1 << 3)) {
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at91_set_B_periph(AT91_PIN_PD9, 1);
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}
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if (cs_mask & (1 << 4)) {
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at91_set_gpio_output(AT91_PIN_PA28, 1);
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}
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if (cs_mask & (1 << 5)) {
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at91_set_gpio_output(AT91_PIN_PB7, 1);
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}
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if (cs_mask & (1 << 6)) {
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at91_set_gpio_output(AT91_PIN_PD8, 1);
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}
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if (cs_mask & (1 << 7)) {
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at91_set_gpio_output(AT91_PIN_PD9, 1);
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}
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}
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#endif
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