upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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295 lines
6.6 KiB
295 lines
6.6 KiB
/*
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* Copyright 2004 Freescale Semiconductor.
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* Jeff Brown (jeffrey@freescale.com)
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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#include <spd.h>
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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extern void ft_cpu_setup(void *blob, bd_t *bd);
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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extern long int spd_sdram(void);
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void local_bus_init(void);
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void sdram_init(void);
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long int fixed_sdram(void);
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int board_early_init_f (void)
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{
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return 0;
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}
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int checkboard (void)
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{
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puts("Board: MPC8641HPCN\n");
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#ifdef CONFIG_PCI
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_pex_t *pex1 = &immap->im_pex1;
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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if ((io_sel==2 || io_sel==3 || io_sel==5 \
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|| io_sel==6 || io_sel==7 || io_sel==0xF)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
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debug ("PCI-EXPRESS 1: %s \n",
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pex1_agent ? "Agent" : "Host");
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debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
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if (pex1->pme_msg_det) {
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pex1->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",
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pex1->pme_msg_det);
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}
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debug ("\n");
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} else {
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printf ("PCI-EXPRESS 1: Disabled\n");
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}
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#else
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printf("PCI-EXPRESS1: Disabled\n");
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#endif
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/*
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* Initialize local bus.
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*/
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local_bus_init();
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return 0;
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}
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long int
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initdram(int board_type)
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{
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long dram_size = 0;
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extern long spd_sdram (void);
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram ();
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#else
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dram_size = fixed_sdram ();
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#endif
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#if defined(CFG_RAMBOOT)
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puts(" DDR: ");
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return dram_size;
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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puts(" DDR: ");
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return dram_size;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_lbc_t *lbc = &immap->im_lbc;
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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/*
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* Errata LBC11.
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* Fix Local Bus clock glitch when DLL is enabled.
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*
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* If localbus freq is < 66Mhz, DLL bypass mode must be used.
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* If localbus freq is > 133Mhz, DLL can be safely enabled.
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* Between 66 and 133, the DLL is enabled with an override workaround.
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*/
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get_sys_info(&sysinfo);
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clkdiv = lbc->lcrr & 0x0f;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram(void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("SDRAM test passed.\n");
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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long int fixed_sdram(void)
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{
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#if !defined(CFG_RAMBOOT)
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_ddr_t *ddr= &immap->im_ddr1;
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ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
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ddr->cs0_config = CFG_DDR_CS0_CONFIG;
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ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
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ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
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ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
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ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
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ddr->sdram_mode_1 = CFG_DDR_MODE_1;
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ddr->sdram_mode_2 = CFG_DDR_MODE_2;
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ddr->sdram_interval = CFG_DDR_INTERVAL;
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ddr->sdram_data_init = CFG_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
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ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
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ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_disable = 0x0000008D;
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ddr->err_sbe = 0x00ff0000;
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#endif
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asm("sync;isync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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/* Enable ECC checking */
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ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
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#else
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ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
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ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
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#endif
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asm("sync; isync");
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udelay(500);
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#endif
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return CFG_SDRAM_SIZE * 1024 * 1024;
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_fsl86xxads_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
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} },
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{ }
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};
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#endif
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static struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_mpc86xxcts_config_table,
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#endif
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};
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#endif /* CONFIG_PCI */
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void
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pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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extern void pci_mpc86xx_init(struct pci_controller *hose);
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pci_mpc86xx_init(&hose);
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#endif /* CONFIG_PCI */
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}
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#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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u32 *p;
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int len;
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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}
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#endif
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