upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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85 lines
2.4 KiB
85 lines
2.4 KiB
/*
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* Copyright (C) 2012 Samsung Electronics
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* R. Chadrasekar <rcsekar@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __WM8994_H__
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#define __WM8994_H__
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/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
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#define WM8994_SYSCLK_MCLK1 1
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#define WM8994_SYSCLK_MCLK2 2
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#define WM8994_SYSCLK_FLL1 3
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#define WM8994_SYSCLK_FLL2 4
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/* Avilable audi interface ports in wm8994 codec */
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enum en_audio_interface {
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WM8994_AIF1 = 1,
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WM8994_AIF2,
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WM8994_AIF3
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};
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/* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */
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#define WM8994_SYSCLK_OPCLK 5
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#define WM8994_FLL1 1
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#define WM8994_FLL2 2
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#define WM8994_FLL_SRC_MCLK1 1
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#define WM8994_FLL_SRC_MCLK2 2
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#define WM8994_FLL_SRC_LRCLK 3
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#define WM8994_FLL_SRC_BCLK 4
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/* maximum available digital interfac in the dac to configure */
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#define WM8994_MAX_AIF 2
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#define WM8994_MAX_INPUT_CLK_FREQ 13500000
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#define WM8994_ID 0x8994
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enum wm8994_vmid_mode {
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WM8994_VMID_NORMAL,
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WM8994_VMID_FORCE,
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};
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/* wm 8994 family devices */
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enum wm8994_type {
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WM8994 = 0,
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WM8958 = 1,
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WM1811 = 2,
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};
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/*
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* intialise wm8994 sound codec device for the given configuration
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*
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* @param blob FDT node for codec values
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* @param aif_id enum value of codec interface port in which
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* soc i2s is connected
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* @param sampling_rate Sampling rate ranges between from 8khz to 96khz
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* @param mclk_freq Master clock frequency.
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* @param bits_per_sample bits per Sample can be 16 or 24
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* @param channels Number of channnels, maximum 2
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*
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* @returns -1 for error and 0 Success.
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*/
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int wm8994_init(const void *blob, enum en_audio_interface aif_id,
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int sampling_rate, int mclk_freq,
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int bits_per_sample, unsigned int channels);
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#endif /*__WM8994_H__ */
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