upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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239 lines
6.6 KiB
239 lines
6.6 KiB
/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Configuation settings for the Zylonite board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
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#define CONFIG_ZYLONITE 1 /* Zylonite board */
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/* #define CONFIG_LCD 1 */
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#ifdef CONFIG_LCD
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#define CONFIG_SHARP_LM8V31
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#endif
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#undef CONFIG_MMC
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#define BOARD_LATE_INIT 1
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#undef CONFIG_SKIP_RELOCATE_UBOOT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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#undef TURN_ON_ETHERNET
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#ifdef TURN_ON_ETHERNET
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# define CONFIG_SMC91111 1
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# define CONFIG_SMC91111_BASE 0x14000300
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# define CONFIG_SMC91111_EXT_PHY
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# define CONFIG_SMC_USE_32_BIT
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# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
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#endif
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/*
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* select serial console configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#ifdef TURN_ON_ETHERNET
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#define CONFIG_CMD_PING
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#else
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_NAND
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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#endif
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#define CONFIG_BOOTDELAY -1
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_IPADDR 192.168.0.21
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#define CONFIG_SERVERIP 192.168.0.250
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#define CONFIG_BOOTCOMMAND "bootm 80000"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_TIMESTAMP
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
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#else
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#endif
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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#define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
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#define CONFIG_SYS_HZ 1000
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/* Monahans Core Frequency */
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#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
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#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#ifdef CONFIG_MMC
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#define CONFIG_PXA_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_SYS_MMC_BASE 0xF0000000
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#endif
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
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#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
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#undef CONFIG_SYS_SKIP_DRAM_SCRUB
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/*
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* NAND Flash
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*/
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#define CONFIG_SYS_NAND0_BASE 0x0
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#undef CONFIG_SYS_NAND1_BASE
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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/* nand timeout values */
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#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
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#define CONFIG_SYS_NAND_OTHER_TO 100
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#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
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#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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/* NAND Timing Parameters (in ns) */
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#define NAND_TIMING_tCH 10
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#define NAND_TIMING_tCS 0
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#define NAND_TIMING_tWH 20
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#define NAND_TIMING_tWP 40
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#define NAND_TIMING_tRH 20
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#define NAND_TIMING_tRP 40
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#define NAND_TIMING_tR 11123
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#define NAND_TIMING_tWHR 100
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#define NAND_TIMING_tAR 10
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/* NAND debugging */
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#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
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#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
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#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
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#define CONFIG_MTD_DEBUG
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#define CONFIG_MTD_DEBUG_VERBOSE 1
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#define CONFIG_SYS_NO_FLASH 1
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_OFFSET_REDUND 0x44000
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#define CONFIG_ENV_SIZE 0x4000
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#endif /* __CONFIG_H */
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