upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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71 lines
1.6 KiB
71 lines
1.6 KiB
#ifndef _ST_PINCFG_H_
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#define _ST_PINCFG_H_
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/* Alternate functions */
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#define ALT1 1
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#define ALT2 2
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#define ALT3 3
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#define ALT4 4
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#define ALT5 5
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#define ALT6 6
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#define ALT7 7
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/* Output enable */
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#define OE (1 << 27)
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/* Pull Up */
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#define PU (1 << 26)
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/* Open Drain */
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#define OD (1 << 25)
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#define RT (1 << 23)
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#define INVERTCLK (1 << 22)
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#define CLKNOTDATA (1 << 21)
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#define DOUBLE_EDGE (1 << 20)
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#define CLK_A (0 << 18)
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#define CLK_B (1 << 18)
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#define CLK_C (2 << 18)
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#define CLK_D (3 << 18)
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/* User-frendly defines for Pin Direction */
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/* oe = 0, pu = 0, od = 0 */
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#define IN (0)
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/* oe = 0, pu = 1, od = 0 */
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#define IN_PU (PU)
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/* oe = 1, pu = 0, od = 0 */
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#define OUT (OE)
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/* oe = 1, pu = 0, od = 1 */
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#define BIDIR (OE | OD)
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/* oe = 1, pu = 1, od = 1 */
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#define BIDIR_PU (OE | PU | OD)
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/* RETIME_TYPE */
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/*
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* B Mode
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* Bypass retime with optional delay parameter
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*/
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#define BYPASS (0)
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/*
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* R0, R1, R0D, R1D modes
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* single-edge data non inverted clock, retime data with clk
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*/
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#define SE_NICLK_IO (RT)
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/*
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* RIV0, RIV1, RIV0D, RIV1D modes
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* single-edge data inverted clock, retime data with clk
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*/
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#define SE_ICLK_IO (RT | INVERTCLK)
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/*
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* R0E, R1E, R0ED, R1ED modes
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* double-edge data, retime data with clk
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*/
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#define DE_IO (RT | DOUBLE_EDGE)
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/*
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* CIV0, CIV1 modes with inverted clock
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* Retiming the clk pins will park clock & reduce the noise within the core.
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*/
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#define ICLK (RT | CLKNOTDATA | INVERTCLK)
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/*
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* CLK0, CLK1 modes with non-inverted clock
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* Retiming the clk pins will park clock & reduce the noise within the core.
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*/
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#define NICLK (RT | CLKNOTDATA)
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#endif /* _ST_PINCFG_H_ */
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