upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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101 lines
2.7 KiB
101 lines
2.7 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/**
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* hcWriteWord - write a 16 bit value into the USB controller
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* @base: base address to access the chip registers
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* @value: 16 bit value to write into register @offset
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* @offset: register to write the @value into
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*
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*/
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static void inline hcWriteWord (unsigned long base, unsigned int value,
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unsigned int offset)
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{
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out_le16 ((volatile u16*)(base + 2), offset | 0x80);
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out_le16 ((volatile u16*)base, value);
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}
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/**
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* hcWriteDWord - write a 32 bit value into the USB controller
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* @base: base address to access the chip registers
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* @value: 32 bit value to write into register @offset
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* @offset: register to write the @value into
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*
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*/
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static void inline hcWriteDWord (unsigned long base, unsigned long value,
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unsigned int offset)
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{
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out_le16 ((volatile u16*)(base + 2), offset | 0x80);
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out_le16 ((volatile u16*)base, value);
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out_le16 ((volatile u16*)base, value >> 16);
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}
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/**
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* hcReadWord - read a 16 bit value from the USB controller
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* @base: base address to access the chip registers
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* @offset: register to read from
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*
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* Returns the readed register value
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*/
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static unsigned int inline hcReadWord (unsigned long base, unsigned int offset)
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{
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out_le16 ((volatile u16*)(base + 2), offset);
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return (in_le16 ((volatile u16*)base));
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}
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/**
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* hcReadDWord - read a 32 bit value from the USB controller
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* @base: base address to access the chip registers
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* @offset: register to read from
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*
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* Returns the readed register value
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*/
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static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset)
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{
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unsigned long val, val16;
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out_le16 ((volatile u16*)(base + 2), offset);
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val = in_le16((volatile u16*)base);
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val16 = in_le16((volatile u16*)base);
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return (val | (val16 << 16));
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}
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/* control and status registers isp1161 */
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#define HcRevision 0x00
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#define HcControl 0x01
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#define HcCommandStatus 0x02
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#define HcInterruptStatus 0x03
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#define HcInterruptEnable 0x04
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#define HcInterruptDisable 0x05
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#define HcFmInterval 0x0D
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#define HcFmRemaining 0x0E
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#define HcFmNumber 0x0F
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#define HcLSThreshold 0x11
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#define HcRhDescriptorA 0x12
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#define HcRhDescriptorB 0x13
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#define HcRhStatus 0x14
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#define HcRhPortStatus1 0x15
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#define HcRhPortStatus2 0x16
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#define HcHardwareConfiguration 0x20
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#define HcDMAConfiguration 0x21
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#define HcTransferCounter 0x22
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#define HcuPInterrupt 0x24
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#define HcuPInterruptEnable 0x25
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#define HcChipID 0x27
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#define HcScratch 0x28
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#define HcSoftwareReset 0x29
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#define HcITLBufferLength 0x2A
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#define HcATLBufferLength 0x2B
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#define HcBufferStatus 0x2C
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#define HcReadBackITL0Length 0x2D
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#define HcReadBackITL1Length 0x2E
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#define HcITLBufferPort 0x40
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#define HcATLBufferPort 0x41
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