upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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96 lines
1.8 KiB
96 lines
1.8 KiB
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/immap_85xx.h>
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#include "sleep.h"
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#ifdef CONFIG_U_QE
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#include "../../../drivers/qe/qe.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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void __weak board_mem_sleep_setup(void)
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{
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}
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void __weak board_sleep_prepare(void)
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{
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}
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bool is_warm_boot(void)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
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return 1;
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return 0;
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}
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void fsl_dp_disable_console(void)
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{
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gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
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}
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/*
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* When wakeup from deep sleep, the first 128 bytes space
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* will be used to do DDR training which corrupts the data
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* in there. This function will restore them.
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*/
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static void dp_ddr_restore(void)
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{
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u64 *src, *dst;
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int i;
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
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/* get the address of ddr date from SPARECR3 */
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src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
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dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
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for (i = 0; i < DDR_BUFF_LEN / 8; i++)
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*dst-- = *src--;
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flush_dcache();
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}
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static void dp_resume_prepare(void)
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{
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dp_ddr_restore();
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board_sleep_prepare();
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l2cache_init();
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#if defined(CONFIG_RAMBOOT_PBL)
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disable_cpc_sram();
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#endif
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enable_cpc();
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#ifdef CONFIG_U_QE
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u_qe_resume();
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#endif
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}
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int fsl_dp_resume(void)
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{
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u32 start_addr;
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void (*kernel_resume)(void);
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
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if (!is_warm_boot())
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return 0;
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dp_resume_prepare();
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/* Get the entry address and jump to kernel */
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start_addr = in_be32(&scfg->sparecr[1]);
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debug("Entry address is 0x%08x\n", start_addr);
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kernel_resume = (void (*)(void))start_addr;
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kernel_resume();
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return 0;
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}
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