upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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213 lines
7.5 KiB
213 lines
7.5 KiB
/*
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* (C) Copyright 2000-2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
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/* ...or on a SYCAMORE board */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME walnut
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_PPC_OLD \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fff80000\0" \
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"ramdisk_addr=fff80000\0" \
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""
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_HAS_ETH0 1
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#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SNTP
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#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
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/*
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* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
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* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
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* The Linux BASE_BAUD define should match this configuration.
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* baseBaud = cpuClock/(uartDivisor*16)
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* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
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* set Linux BASE_BAUD to 403200.
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
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#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
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#define CONFIG_SYS_BASE_BAUD 691200
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/*-----------------------------------------------------------------------
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* I2C stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
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#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFFF80000
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/*
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* Define here the location of the environment variables (FLASH or NVRAM).
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* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
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* supported for backward compatibility.
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*/
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#if 1
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_ADDR0 0x5555
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#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* NVRAM organization
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*/
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
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#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
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#ifdef CONFIG_ENV_IS_IN_NVRAM
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#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
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#endif
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (Flash Bank 0) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x9B015480
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#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
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#define CONFIG_SYS_EBC_PB1AP 0x02815480
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#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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#define CONFIG_SYS_EBC_PB2AP 0x04815A80
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#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
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#define CONFIG_SYS_EBC_PB3AP 0x01815280
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#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
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#define CONFIG_SYS_EBC_PB7AP 0x01815280
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#define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
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/*-----------------------------------------------------------------------
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* External peripheral base address
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
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#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
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#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Definitions for Serial Presence Detect EEPROM address
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* (to get SDRAM settings)
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*/
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#define SPD_EEPROM_ADDRESS 0x50
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#endif /* __CONFIG_H */
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