upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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37 lines
1021 B
37 lines
1021 B
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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*/
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#ifndef __BOARD_CLK_LIB_H
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#define __BOARD_CLK_LIB_H
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#include <common.h>
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enum clk_ctl_ops {
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CLK_SET = BIT(0), /* set frequency */
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CLK_GET = BIT(1), /* get frequency */
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CLK_ON = BIT(2), /* enable clock */
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CLK_OFF = BIT(3), /* disable clock */
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CLK_PRINT = BIT(4), /* print frequency */
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CLK_MHZ = BIT(5) /* all values in MHZ instead of HZ */
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};
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/*
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* Depending on the clk_ctl_ops enable / disable /
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* set clock rate from 'rate' argument / read clock to 'rate' argument /
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* print clock rate. If CLK_MHZ flag set in clk_ctl_ops 'rate' is in MHz,
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* otherwise - in Hz.
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*
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* This function expects "clk-fmeas" node in device tree:
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* / {
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* clk-fmeas {
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* clocks = <&cpu_pll>, <&sys_pll>;
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* clock-names = "cpu-pll", "sys-pll";
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* };
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* };
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*/
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int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl);
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#endif /* __BOARD_CLK_LIB_H */
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