upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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659 lines
24 KiB
659 lines
24 KiB
/*
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2001
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* Advent Networks, Inc. <http://www.adventnetworks.com>
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* Jay Monkman <jtm@smoothsmoothie.com>
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*
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* (C) Copyright 2001
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* Advent Networks, Inc. <http://www.adventnetworks.com>
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* Oliver Brown <oliverb@alumni.utexas.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*********************************************************************/
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/* DESCRIPTION:
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* This file contains the board routines for the GW8260 board.
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*
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* MODULE DEPENDENCY:
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* None
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*
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* RESTRICTIONS/LIMITATIONS:
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* None
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*
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* Copyright (c) 2001, Advent Networks, Inc.
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*/
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/*********************************************************************/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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/*
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* I/O Port configuration table
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*
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* TP14 */
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/* PA30 */ { 1, 1, 1, 1, 0, 0 }, /* US_RTS */
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/* PA29 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_DATA */
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/* PA28 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_CLK */
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/* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* TP12 */
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/* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* IO_STATUS */
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/* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CLOCK */
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/* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CONFIG */
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/* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DONE */
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/* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DATA */
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/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD3 */
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/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD2 */
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/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD1 */
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/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD0 */
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/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD0 */
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/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD1 */
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/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD2 */
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/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD3 */
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/* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE7 */
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/* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE6 */
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/* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE5 */
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/* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE4 */
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/* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE3 */
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/* PA8 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE2 */
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/* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* LSSI_IN */
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/* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE0 */
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/* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* DEMOD_RESET_ */
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/* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* MOD_RESET_ */
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/* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* IO_RESET */
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/* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* TX_ENABLE */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* RX_LOCK */
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/* PA0 */ { 1, 0, 0, 1, 0, 1 } /* MPC_RESET_ */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FETH0_TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD3 */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD2 */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD1 */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD0 */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD0 */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD1 */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD2 */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD3 */
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/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_DV */
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/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_ER */
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/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_ER */
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/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_EN */
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/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_COL */
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/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_CRS */
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/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD3 */
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/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD2 */
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/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD1 */
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/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD0 */
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/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD0 */
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/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD1 */
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/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD2 */
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/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD3 */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_RESET_ */
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/* PC30 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_PAUSE_ */
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/* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW1 */
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/* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW0 */
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/* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* TP13 */
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/* PC26 */ { 1, 0, 0, 0, 0, 0 }, /* RXDECDFLG */
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/* PC25 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFAIL */
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/* PC24 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFLG */
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/* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* WD_TCL */
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/* PC22 */ { 1, 0, 0, 1, 0, 0 }, /* WD_EN */
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/* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* US_TXCLK */
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/* PC20 */ { 1, 0, 0, 0, 0, 0 }, /* DS_RXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_CLK */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_TX_CLK */
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/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_CLK */
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/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_TX_CLK */
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/* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* TX_SHUTDOWN_ */
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/* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* RS_232_DTR_ */
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/* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* TXERR */
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/* PC12 */ { 1, 0, 0, 1, 0, 1 }, /* FETH1_MDDIS */
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/* PC11 */ { 1, 0, 0, 1, 0, 1 }, /* FETH0_MDDIS */
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */
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/* PC9 */ { 1, 0, 0, 1, 1, 1 }, /* MDIO */
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/* PC8 */ { 1, 0, 0, 1, 1, 1 }, /* SER_NUM */
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/* PC7 */ { 1, 1, 0, 0, 0, 0 }, /* US_CTS */
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/* PC6 */ { 1, 1, 0, 0, 0, 0 }, /* DS_CD_ */
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/* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* FETH1_PWRDWN */
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/* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* FETH0_PWRDWN */
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/* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED3 */
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/* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED2 */
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/* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED1 */
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/* PC0 */ { 1, 0, 0, 1, 0, 1 }, /* MPULED0 */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
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/* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
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/* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
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/* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
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/* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SCL */
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/* PD13 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED7 */
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/* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED6 */
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/* PD11 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED5 */
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/* PD10 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED4 */
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* RS232_TXD */
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* RD232_RXD */
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/* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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/*********************************************************************/
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/* NAME: checkboard() - Displays the board type and serial number */
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/* */
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/* OUTPUTS: */
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/* Displays the board type and serial number */
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/* */
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/* RETURNS: */
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/* Always returns 1 */
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/* */
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/* RESTRICTIONS/LIMITATIONS: */
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/* */
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/* */
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/*********************************************************************/
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int checkboard(void)
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{
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char *str;
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puts ("Board: Advent Networks gw8260\n");
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str = getenv("serial#");
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if (str != NULL) {
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printf("SN: %s\n", str);
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}
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return 0;
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}
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#if defined (CFG_DRAM_TEST)
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/*********************************************************************/
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/* NAME: move64() - moves a double word (64-bit) */
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/* */
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/* DESCRIPTION: */
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/* this function performs a double word move from the data at */
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/* the source pointer to the location at the destination pointer. */
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/* */
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/* INPUTS: */
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/* unsigned long long *src - pointer to data to move */
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/* */
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/* OUTPUTS: */
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/* unsigned long long *dest - pointer to locate to move data */
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/* */
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/* RETURNS: */
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/* None */
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/* */
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/* RESTRICTIONS/LIMITATIONS: */
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/* May cloober fr0. */
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/* */
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/*********************************************************************/
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static void move64(unsigned long long *src, unsigned long long *dest)
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{
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asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
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"stfd 0, 0(4)" /* *dest = fpr0 */
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: : : "fr0" ); /* Clobbers fr0 */
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return;
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}
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#if defined (CFG_DRAM_TEST_DATA)
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unsigned long long pattern[]= {
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0xaaaaaaaaaaaaaaaa,
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0xcccccccccccccccc,
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0xf0f0f0f0f0f0f0f0,
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0xff00ff00ff00ff00,
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0xffff0000ffff0000,
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0xffffffff00000000,
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0x00000000ffffffff,
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0x0000ffff0000ffff,
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0x00ff00ff00ff00ff,
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0x0f0f0f0f0f0f0f0f,
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0x3333333333333333,
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0x5555555555555555};
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/*********************************************************************/
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/* NAME: mem_test_data() - test data lines for shorts and opens */
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/* */
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/* DESCRIPTION: */
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/* Tests data lines for shorts and opens by forcing adjacent data */
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/* to opposite states. Because the data lines could be routed in */
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/* an arbitrary manner the must ensure test patterns ensure that */
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/* every case is tested. By using the following series of binary */
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/* patterns every combination of adjacent bits is test regardless */
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/* of routing. */
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/* */
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/* ...101010101010101010101010 */
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/* ...110011001100110011001100 */
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/* ...111100001111000011110000 */
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/* ...111111110000000011111111 */
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/* */
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/* Carrying this out, gives us six hex patterns as follows: */
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/* */
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/* 0xaaaaaaaaaaaaaaaa */
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/* 0xcccccccccccccccc */
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/* 0xf0f0f0f0f0f0f0f0 */
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/* 0xff00ff00ff00ff00 */
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/* 0xffff0000ffff0000 */
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/* 0xffffffff00000000 */
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/* */
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/* The number test patterns will always be given by: */
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/* */
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/* log(base 2)(number data bits) = log2 (64) = 6 */
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/* */
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/* To test for short and opens to other signals on our boards. we */
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/* simply */
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/* test with the 1's complemnt of the paterns as well. */
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/* */
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/* OUTPUTS: */
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/* Displays failing test pattern */
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/* */
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/* RETURNS: */
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/* 0 - Passed test */
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/* 1 - Failed test */
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/* */
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/* RESTRICTIONS/LIMITATIONS: */
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/* Assumes only one one SDRAM bank */
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/* */
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/*********************************************************************/
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int mem_test_data(void)
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{
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unsigned long long * pmem =
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(unsigned long long *)CFG_SDRAM_BASE ;
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unsigned long long temp64;
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int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
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int i;
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unsigned int hi, lo;
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for ( i = 0; i < num_patterns; i++) {
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move64(&(pattern[i]), pmem);
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move64(pmem, &temp64);
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/* hi = (temp64>>32) & 0xffffffff; */
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/* lo = temp64 & 0xffffffff; */
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/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
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hi = (pattern[i]>>32) & 0xffffffff;
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lo = pattern[i] & 0xffffffff;
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/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
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if (temp64 != pattern[i]){
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printf ("\n Data Test Failed, pattern 0x%08x%08x", hi, lo);
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return 1;
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}
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}
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return 0;
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}
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#endif /* CFG_DRAM_TEST_DATA */
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#if defined (CFG_DRAM_TEST_ADDRESS)
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/*********************************************************************/
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/* NAME: mem_test_address() - test address lines */
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/* */
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/* DESCRIPTION: */
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/* This function performs a test to verify that each word im */
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/* memory is uniquly addressable. The test sequence is as follows: */
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/* */
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/* 1) write the address of each word to each word. */
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/* 2) verify that each location equals its address */
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/* */
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/* OUTPUTS: */
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/* Displays failing test pattern and address */
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/* */
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/* RETURNS: */
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/* 0 - Passed test */
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/* 1 - Failed test */
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/* */
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/* RESTRICTIONS/LIMITATIONS: */
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/* */
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/* */
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/*********************************************************************/
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int mem_test_address(void)
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{
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volatile unsigned int * pmem = (volatile unsigned int *)CFG_SDRAM_BASE ;
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const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024)/4;
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unsigned int i;
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/* write address to each location */
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for ( i = 0; i < size; i++) {
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pmem[i] = i;
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}
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/* verify each loaction */
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for ( i = 0; i < size; i++) {
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if (pmem[i] != i) {
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printf("\n Address Test Failed at 0x%x", i);
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return 1;
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}
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}
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return 0;
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}
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#endif /* CFG_DRAM_TEST_ADDRESS */
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#if defined (CFG_DRAM_TEST_WALK)
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/*********************************************************************/
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/* NAME: mem_march() - memory march */
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/* */
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/* DESCRIPTION: */
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/* Marches up through memory. At each location verifies rmask if */
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|
/* read = 1. At each location write wmask if write = 1. Displays */
|
|
/* failing address and pattern. */
|
|
/* */
|
|
/* INPUTS: */
|
|
/* volatile unsigned long long * base - start address of test */
|
|
/* unsigned int size - number of dwords(64-bit) to test */
|
|
/* unsigned long long rmask - read verify mask */
|
|
/* unsigned long long wmask - wrtie verify mask */
|
|
/* short read - verifies rmask if read = 1 */
|
|
/* short write - writes wmask if write = 1 */
|
|
/* */
|
|
/* OUTPUTS: */
|
|
/* Displays failing test pattern and address */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* 0 - Passed test */
|
|
/* 1 - Failed test */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* */
|
|
/* */
|
|
/*********************************************************************/
|
|
int mem_march(volatile unsigned long long * base,
|
|
unsigned int size,
|
|
unsigned long long rmask,
|
|
unsigned long long wmask,
|
|
short read,
|
|
short write)
|
|
{
|
|
unsigned int i;
|
|
unsigned long long temp;
|
|
unsigned int hitemp, lotemp, himask, lomask;
|
|
|
|
for (i = 0 ; i < size ; i++) {
|
|
if (read != 0) {
|
|
/* temp = base[i]; */
|
|
move64 ((unsigned long long *)&(base[i]), &temp);
|
|
if (rmask != temp) {
|
|
hitemp = (temp>>32) & 0xffffffff;
|
|
lotemp = temp & 0xffffffff;
|
|
himask = (rmask>>32) & 0xffffffff;
|
|
lomask = rmask & 0xffffffff;
|
|
|
|
printf("\n Walking one's test failed: address = 0x%08x,"
|
|
"\n\texpected 0x%08x%08x, found 0x%08x%08x",
|
|
i<<3, himask, lomask, hitemp, lotemp);
|
|
return 1;
|
|
}
|
|
}
|
|
if ( write != 0 ) {
|
|
/* base[i] = wmask; */
|
|
move64 (&wmask, (unsigned long long *)&(base[i]));
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
#endif /* CFG_DRAM_TEST_WALK */
|
|
|
|
/*********************************************************************/
|
|
/* NAME: mem_test_walk() - a simple walking ones test */
|
|
/* */
|
|
/* DESCRIPTION: */
|
|
/* Performs a walking ones through entire physical memory. The */
|
|
/* test uses as series of memory marches, mem_march(), to verify */
|
|
/* and write the test patterns to memory. The test sequence is as */
|
|
/* follows: */
|
|
/* 1) march writing 0000...0001 */
|
|
/* 2) march verifying 0000...0001 , writing 0000...0010 */
|
|
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
|
|
/* the write mask equals 1000...0000 */
|
|
/* 4) march verifying 1000...0000 */
|
|
/* The test fails if any of the memory marches return a failure. */
|
|
/* */
|
|
/* OUTPUTS: */
|
|
/* Displays which pass on the memory test is executing */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* 0 - Passed test */
|
|
/* 1 - Failed test */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* */
|
|
/* */
|
|
/*********************************************************************/
|
|
int mem_test_walk(void)
|
|
{
|
|
unsigned long long mask;
|
|
volatile unsigned long long * pmem =
|
|
(volatile unsigned long long *)CFG_SDRAM_BASE ;
|
|
const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024)/8;
|
|
|
|
unsigned int i;
|
|
mask = 0x01;
|
|
|
|
printf("Initial Pass");
|
|
mem_march(pmem,size,0x0,0x1,0,1);
|
|
|
|
printf("\b\b\b\b\b\b\b\b\b\b\b\b");
|
|
printf(" ");
|
|
printf("\b\b\b\b\b\b\b\b\b\b\b\b");
|
|
|
|
for (i = 0 ; i < 63 ; i++) {
|
|
printf("Pass %2d", i+2);
|
|
if ( mem_march(pmem,size, mask,mask << 1, 1, 1) != 0 ){
|
|
/*printf("mask: 0x%x, pass: %d, ", mask, i);*/
|
|
return 1;
|
|
}
|
|
mask = mask<<1;
|
|
printf("\b\b\b\b\b\b\b");
|
|
}
|
|
|
|
printf("Last Pass");
|
|
if (mem_march(pmem, size, 0, mask, 0, 1) != 0) {
|
|
/* printf("mask: 0x%x", mask); */
|
|
return 1;
|
|
}
|
|
printf("\b\b\b\b\b\b\b\b\b");
|
|
printf(" ");
|
|
printf("\b\b\b\b\b\b\b\b\b");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*********************************************************************/
|
|
/* NAME: testdram() - calls any enabled memory tests */
|
|
/* */
|
|
/* DESCRIPTION: */
|
|
/* Runs memory tests if the environment test variables are set to */
|
|
/* 'y'. */
|
|
/* */
|
|
/* INPUTS: */
|
|
/* testdramdata - If set to 'y', data test is run. */
|
|
/* testdramaddress - If set to 'y', address test is run. */
|
|
/* testdramwalk - If set to 'y', walking ones test is run */
|
|
/* */
|
|
/* OUTPUTS: */
|
|
/* None */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* 0 - Passed test */
|
|
/* 1 - Failed test */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* */
|
|
/* */
|
|
/*********************************************************************/
|
|
int testdram(void)
|
|
{
|
|
char *s;
|
|
int rundata, runaddress, runwalk;
|
|
|
|
s = getenv ("testdramdata");
|
|
rundata = (s && (*s == 'y')) ? 1 : 0;
|
|
s = getenv ("testdramaddress");
|
|
runaddress = (s && (*s == 'y')) ? 1 : 0;
|
|
s = getenv ("testdramwalk");
|
|
runwalk = (s && (*s == 'y')) ? 1 : 0;
|
|
|
|
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
|
|
printf("Testing RAM ... ");
|
|
}
|
|
#ifdef CFG_DRAM_TEST_DATA
|
|
if (rundata == 1) {
|
|
if (mem_test_data() == 1){
|
|
return 1;
|
|
}
|
|
}
|
|
#endif
|
|
#ifdef CFG_DRAM_TEST_ADDRESS
|
|
if (runaddress == 1) {
|
|
if (mem_test_address() == 1){
|
|
return 1;
|
|
}
|
|
}
|
|
#endif
|
|
#ifdef CFG_DRAM_TEST_WALK
|
|
if (runwalk == 1) {
|
|
if (mem_test_walk() == 1){
|
|
return 1;
|
|
}
|
|
}
|
|
#endif
|
|
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
|
|
printf("passed");
|
|
}
|
|
return 0;
|
|
|
|
}
|
|
#endif /* CFG_DRAM_TEST */
|
|
|
|
/*********************************************************************/
|
|
/* NAME: initdram() - initializes SDRAM controller */
|
|
/* */
|
|
/* DESCRIPTION: */
|
|
/* Initializes the MPC8260's SDRAM controller. */
|
|
/* */
|
|
/* INPUTS: */
|
|
/* CFG_IMMR - MPC8260 Internal memory map */
|
|
/* CFG_SDRAM_BASE - Physical start address of SDRAM */
|
|
/* CFG_PSDMR - SDRAM mode register */
|
|
/* CFG_MPTPR - Memory refresh timer prescaler register */
|
|
/* CFG_SDRAM0_SIZE - SDRAM size */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* SDRAM size in bytes */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* */
|
|
/* */
|
|
/*********************************************************************/
|
|
long int initdram(int board_type)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile memctl8260_t *memctl = &immap->im_memctl;
|
|
volatile uchar c = 0, *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
|
|
ulong psdmr = CFG_PSDMR;
|
|
int i;
|
|
|
|
/*
|
|
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
|
*
|
|
* "At system reset, initialization software must set up the
|
|
* programmable parameters in the memory controller banks registers
|
|
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
|
* system software should execute the following initialization sequence
|
|
* for each SDRAM device.
|
|
*
|
|
* 1. Issue a PRECHARGE-ALL-BANKS command
|
|
* 2. Issue eight CBR REFRESH commands
|
|
* 3. Issue a MODE-SET command to initialize the mode register
|
|
*
|
|
* The initial commands are executed by setting P/LSDMR[OP] and
|
|
* accessing the SDRAM with a single-byte transaction."
|
|
*
|
|
* The appropriate BRx/ORx registers have already been set when we
|
|
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
|
|
*/
|
|
|
|
memctl->memc_psrt = CFG_PSRT;
|
|
memctl->memc_mptpr = CFG_MPTPR;
|
|
|
|
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
|
|
*ramaddr = c;
|
|
|
|
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
|
|
for (i = 0; i < 8; i++){
|
|
*ramaddr = c;
|
|
}
|
|
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
|
|
*ramaddr = c;
|
|
|
|
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
|
*ramaddr = c;
|
|
|
|
/* return total ram size */
|
|
return (CFG_SDRAM0_SIZE * 1024 * 1024);
|
|
}
|
|
|
|
/*********************************************************************/
|
|
/* End of gw8260.c */
|
|
/*********************************************************************/
|
|
|