upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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314 lines
8.6 KiB
314 lines
8.6 KiB
/*
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* Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
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* Copyright (C) 2008-2009 MontaVista Software, Inc.
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*
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* Authors: Tony Li <tony.li@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PCIE_MAX_BUSES 2
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#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
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static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
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{
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int bus = PCI_BUS(dev) - hose->first_busno;
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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pex83xx_t *pex = &immr->pciexp[bus];
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struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
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u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
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u32 dev_base = bus << 24 | devfn << 16;
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if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
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return -1;
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/*
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* Workaround for the HW bug: for Type 0 configure transactions the
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* PCI-E controller does not check the device number bits and just
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* assumes that the device number bits are 0.
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*/
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if (devfn & 0xf8)
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return -1;
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out_le32(&out_win->tarl, dev_base);
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return 0;
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}
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#define cfg_read(val, addr, type, op) \
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do { *val = op((type)(addr)); } while (0)
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#define cfg_write(val, addr, type, op) \
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do { op((type *)(addr), (val)); } while (0)
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#define PCIE_OP(rw, size, type, op) \
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static int pcie_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, \
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type val) \
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{ \
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int ret; \
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\
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ret = mpc83xx_pcie_remap_cfg(hose, dev); \
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if (ret) \
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return ret; \
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cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
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return 0; \
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}
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PCIE_OP(read, byte, u8 *, in_8)
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PCIE_OP(read, word, u16 *, in_le16)
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PCIE_OP(read, dword, u32 *, in_le32)
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PCIE_OP(write, byte, u8, out_8)
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PCIE_OP(write, word, u16, out_le16)
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PCIE_OP(write, dword, u32, out_le32)
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static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
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u8 link)
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{
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extern void disable_addr_trans(void); /* start.S */
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static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
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static int max_bus;
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struct pci_controller *hose = &pcie_hose[bus];
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int i;
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/*
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* There are no spare BATs to remap all PCI-E windows for U-Boot, so
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* disable translations. In general, this is not great solution, and
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* that's why we don't register PCI-E hoses by default.
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*/
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disable_addr_trans();
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for (i = 0; i < 2; i++, reg++) {
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if (reg->size == 0)
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break;
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hose->regions[i] = *reg;
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hose->region_count++;
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}
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i = hose->region_count++;
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hose->regions[i].bus_start = 0;
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hose->regions[i].phys_start = 0;
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hose->regions[i].size = gd->ram_size;
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hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
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i = hose->region_count++;
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hose->regions[i].bus_start = CONFIG_SYS_IMMR;
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hose->regions[i].phys_start = CONFIG_SYS_IMMR;
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hose->regions[i].size = 0x100000;
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hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
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hose->first_busno = max_bus;
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hose->last_busno = 0xff;
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if (bus == 0)
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hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
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else
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hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
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pci_set_ops(hose,
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pcie_read_config_byte,
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pcie_read_config_word,
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pcie_read_config_dword,
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pcie_write_config_byte,
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pcie_write_config_word,
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pcie_write_config_dword);
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if (!link)
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hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
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pci_register_hose(hose);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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max_bus = hose->last_busno + 1;
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}
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#else
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static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
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u8 link) {}
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#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
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static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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pex83xx_t *pex = &immr->pciexp[bus];
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struct pex_outbound_window *out_win;
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struct pex_inbound_window *in_win;
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void *hose_cfg_base;
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unsigned int ram_sz;
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unsigned int barl;
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unsigned int tar;
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u16 reg16;
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int i;
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/* Enable pex csb bridge inbound & outbound transactions */
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out_le32(&pex->bridge.pex_csb_ctrl,
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in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
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PEX_CSB_CTRL_IBPIOE);
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/* Enable bridge outbound */
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out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
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PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
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PEX_CSB_OBCTRL_CFGWE);
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out_win = &pex->bridge.pex_outbound_win[0];
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if (bus) {
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out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
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CONFIG_SYS_PCIE2_CFG_SIZE);
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out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE);
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} else {
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out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
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CONFIG_SYS_PCIE1_CFG_SIZE);
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out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE);
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}
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out_le32(&out_win->tarl, 0);
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out_le32(&out_win->tarh, 0);
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for (i = 0; i < 2; i++, reg++) {
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u32 ar;
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if (reg->size == 0)
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break;
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out_win = &pex->bridge.pex_outbound_win[i + 1];
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out_le32(&out_win->bar, reg->phys_start);
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out_le32(&out_win->tarl, reg->bus_start);
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out_le32(&out_win->tarh, 0);
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ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE);
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if (reg->flags & PCI_REGION_IO)
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ar |= PEX_OWAR_TYPE_IO;
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else
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ar |= PEX_OWAR_TYPE_MEM;
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out_le32(&out_win->ar, ar);
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}
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out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
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ram_sz = gd->ram_size;
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barl = 0;
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tar = 0;
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i = 0;
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while (ram_sz > 0) {
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in_win = &pex->bridge.pex_inbound_win[i];
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out_le32(&in_win->barl, barl);
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out_le32(&in_win->barh, 0x0);
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out_le32(&in_win->tar, tar);
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if (ram_sz >= 0x10000000) {
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/* The maxium windows size is 256M */
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out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
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PEX_IWAR_TYPE_PF | 0x0FFFF000);
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barl += 0x10000000;
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tar += 0x10000000;
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ram_sz -= 0x10000000;
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} else {
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/* The UM is not clear here.
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* So, round up to even Mb boundary */
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ram_sz = ram_sz >> (20 +
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((ram_sz & 0xFFFFF) ? 1 : 0));
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if (!(ram_sz % 2))
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ram_sz -= 1;
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out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
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PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
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ram_sz = 0;
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}
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i++;
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}
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in_win = &pex->bridge.pex_inbound_win[i];
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out_le32(&in_win->barl, CONFIG_SYS_IMMR);
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out_le32(&in_win->barh, 0);
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out_le32(&in_win->tar, CONFIG_SYS_IMMR);
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out_le32(&in_win->ar, PEX_IWAR_EN |
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PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
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/* Enable the host virtual INTX interrupts */
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out_le32(&pex->bridge.pex_int_axi_misc_enb,
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in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
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/* Hose configure header is memory-mapped */
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hose_cfg_base = (void *)pex;
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get_clocks();
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/* Configure the PCIE controller core clock ratio */
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out_le32(hose_cfg_base + PEX_GCLK_RATIO,
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(((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
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/ 333);
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udelay(1000000);
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/* Do Type 1 bridge configuration */
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out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
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out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
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out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
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/*
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* Write to Command register
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*/
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reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
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PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
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out_le16(hose_cfg_base + PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
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out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
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out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
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printf("PCIE%d: ", bus);
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reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
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if (reg16 >= PCI_LTSSM_L0)
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printf("link\n");
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else
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printf("No link\n");
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mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
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}
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/*
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* The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
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* must have been set to cover all of the requested regions.
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*/
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void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot)
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{
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int i;
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/*
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* Release PCI RST Output signal.
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* Power on to RST high must be at least 100 ms as per PCI spec.
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* On warm boots only 1 ms is required.
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*/
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udelay(warmboot ? 1000 : 100000);
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for (i = 0; i < num_buses; i++)
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mpc83xx_pcie_init_bus(i, reg[i]);
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}
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