upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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525 lines
18 KiB
525 lines
18 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2007 Wind River Systems <www.windriver.com>
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* Copyright 2007 Embedded Specialties, Inc.
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* Joe Hamman <joe.hamman@embeddedspecialties.com>
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*
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* Copyright 2006 Freescale Semiconductor.
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*
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*/
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/*
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* SBC8641D board configuration file
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*
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* Make sure you change the MAC address and other network params first,
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* search for CONFIG_SERVERIP, etc in this file.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
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#ifdef RUN_DIAG
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#define CONFIG_SYS_DIAG_ADDR 0xff800000
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#endif
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#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
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/*
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* virtual address to be used for temporary mappings. There
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* should be 128k free at this VA.
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*/
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#define CONFIG_SYS_SCRATCH_VA 0xe8000000
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
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#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
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#undef CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CACHE_LINE_INTERLEAVING 0x20000000
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#define PAGE_INTERLEAVING 0x21000000
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#define BANK_INTERLEAVING 0x22000000
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#define SUPER_BANK_INTERLEAVING 0x23000000
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#define CONFIG_ALTIVEC 1
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/*
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* L2CR setup -- make sure this is right for your board!
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*/
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#define CONFIG_SYS_L2
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#define L2_INIT 0
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#define L2_ENABLE (L2CR_L2E)
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
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#endif
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
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#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_DIMM_SLOTS_PER_CTLR 2
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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#if defined(CONFIG_SPD_EEPROM)
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/*
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* Determine DDR configuration from I2C interface.
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*/
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#define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
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#define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
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#define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
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#define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
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#else
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/*
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* Manually set up DDR1 & DDR2 parameters
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*/
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#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
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#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 0x00220802
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#define CONFIG_SYS_DDR_TIMING_1 0x38377322
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#define CONFIG_SYS_DDR_TIMING_2 0x002040c7
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#define CONFIG_SYS_DDR_CFG_1A 0x43008008
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#define CONFIG_SYS_DDR_CFG_2 0x24401000
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#define CONFIG_SYS_DDR_MODE_1 0x23c00542
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#define CONFIG_SYS_DDR_MODE_2 0x00000000
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#define CONFIG_SYS_DDR_MODE_CTL 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL 0x05080100
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#define CONFIG_SYS_DDR_DATA_INIT 0x00000000
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#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
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#define CONFIG_SYS_DDR_CFG_1B 0xC3008008
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#define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
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#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
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#define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
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#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
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#define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
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#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
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#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
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#define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
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#define CONFIG_SYS_DDR2_TIMING_0 0x00220802
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#define CONFIG_SYS_DDR2_TIMING_1 0x38377322
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#define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
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#define CONFIG_SYS_DDR2_CFG_1A 0x43008008
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#define CONFIG_SYS_DDR2_CFG_2 0x24401000
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#define CONFIG_SYS_DDR2_MODE_1 0x23c00542
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#define CONFIG_SYS_DDR2_MODE_2 0x00000000
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#define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
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#define CONFIG_SYS_DDR2_INTERVAL 0x05080100
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#define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
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#define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
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#define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
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#endif
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/* #define CONFIG_ID_EEPROM 1
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#define ID_EEPROM_ADDR 0x57 */
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/*
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* The SBC8641D contains 16MB flash space at ff000000.
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*/
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#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
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/* Flash */
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#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
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#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
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/* 64KB EEPROM */
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#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
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#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
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/* EPLD - User switches, board id, LEDs */
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#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
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#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
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/* Local bus SDRAM 128MB */
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#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
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#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
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#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
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#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
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/* Disk on Chip (DOC) 128MB */
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#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
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#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
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/* LCD */
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#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
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#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
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/* Control logic & misc peripherals */
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#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
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#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_PROTECTION
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#undef CONFIG_CLOCKS_IN_MHZ
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#ifndef CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
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#endif
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/*
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* RapidIO MMU
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*/
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#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
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#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
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#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
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#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
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#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
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#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
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#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
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#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
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#if defined(CONFIG_PCI)
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xe0000000
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#define PCI_ENET0_MEMADDR 0xe0000000
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#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
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#endif
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#ifdef CONFIG_SCSI_AHCI
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#define CONFIG_SATA_ULI5288
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
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#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
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#endif
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define CONFIG_TSEC4 1
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#define CONFIG_TSEC4_NAME "eTSEC4"
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#define TSEC1_PHY_ADDR 0x1F
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#define TSEC2_PHY_ADDR 0x00
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#define TSEC3_PHY_ADDR 0x01
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#define TSEC4_PHY_ADDR 0x02
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define TSEC4_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC3_FLAGS TSEC_GIGABIT
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#define TSEC4_FLAGS TSEC_GIGABIT
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#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
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#define CONFIG_ETHPRIME "eTSEC1"
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#endif /* CONFIG_TSEC_ENET */
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/*
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* BAT0 2G Cacheable, non-guarded
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* 0x0000_0000 2G DDR
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*/
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#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
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#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
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/*
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* BAT1 1G Cache-inhibited, guarded
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* 0x8000_0000 512M PCI-Express 1 Memory
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* 0xa000_0000 512M PCI-Express 2 Memory
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* Changed it for operating from 0xd0000000
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*/
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#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
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| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
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/*
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* BAT2 512M Cache-inhibited, guarded
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* 0xc000_0000 512M RapidIO Memory
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*/
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
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| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
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/*
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* BAT3 4M Cache-inhibited, guarded
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* 0xf800_0000 4M CCSR
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*/
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#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
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| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
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#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
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#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
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| BATL_PP_RW | BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
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| BATU_BL_1M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
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| BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
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#endif
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/*
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* BAT4 32M Cache-inhibited, guarded
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* 0xe200_0000 16M PCI-Express 1 I/O
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* 0xe300_0000 16M PCI-Express 2 I/0
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* Note that this is at 0xe0000000
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*/
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#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
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| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
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/*
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* BAT5 128K Cacheable, non-guarded
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* 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
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*/
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#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
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#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
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/*
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* BAT6 32M Cache-inhibited, guarded
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* 0xfe00_0000 32M FLASH
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*/
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#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
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| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
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/* Map the last 1M of flash where we're running from reset */
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#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
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| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
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#define CONFIG_SYS_DBAT7L 0x00000000
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#define CONFIG_SYS_DBAT7U 0x00000000
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#define CONFIG_SYS_IBAT7L 0x00000000
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#define CONFIG_SYS_IBAT7U 0x00000000
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/*
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* Environment
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|
*/
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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|
*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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|
* For booting Linux, the board info and command line data
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|
* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
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/* Cache Configuration */
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#define CONFIG_SYS_DCACHE_SIZE 32768
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
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#endif
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|
#if defined(CONFIG_CMD_KGDB)
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|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
|
|
* Environment Configuration
|
|
*/
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|
#define CONFIG_HAS_ETH0 1
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#define CONFIG_HAS_ETH1 1
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#define CONFIG_HAS_ETH2 1
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#define CONFIG_HAS_ETH3 1
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|
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#define CONFIG_IPADDR 192.168.0.50
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|
|
#define CONFIG_HOSTNAME "sbc8641d"
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|
#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
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|
#define CONFIG_BOOTFILE "uImage"
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|
|
|
#define CONFIG_SERVERIP 192.168.0.2
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|
#define CONFIG_GATEWAYIP 192.168.0.1
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|
#define CONFIG_NETMASK 255.255.255.0
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|
|
|
/* default location for tftp and bootm */
|
|
#define CONFIG_LOADADDR 1000000
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|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
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|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=2000000\0" \
|
|
"ramdiskfile=uRamdisk\0" \
|
|
"dtbaddr=400000\0" \
|
|
"dtbfile=sbc8641d.dtb\0" \
|
|
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
|
|
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
|
|
"maxcpus=1"
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $dtbaddr $dtbfile;" \
|
|
"bootm $loadaddr - $dtbaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $dtbaddr $dtbfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $dtbaddr"
|
|
|
|
#define CONFIG_FLASHBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"bootm ffd00000 ffb00000 ffa00000"
|
|
|
|
#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
|
|
|
|
#endif /* __CONFIG_H */
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|
|