upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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262 lines
6.2 KiB
262 lines
6.2 KiB
/*
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* board/renesas/lager/lager.c
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* This file is lager board support.
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/sh_sdhi.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <mmc.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* CPU frequency setting. Set to 1.4GHz */
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if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
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u32 stat = 0;
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u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
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<< PLL0_STC_BIT;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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do {
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stat = readl(PLLECR) & PLL0ST;
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} while (stat == 0x0);
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}
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/* QoS(Quality-of-Service) Init */
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qos_init();
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}
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#define TMU0_MSTP125 (1 << 25)
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#define SCIF0_MSTP721 (1 << 21)
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#define ETHER_MSTP813 (1 << 13)
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#define MMC1_MSTP305 (1 << 5)
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#define MSTPSR3 0xE6150048
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#define SMSTPCR3 0xE615013C
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#define SDHI0_MSTP314 (1 << 14)
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#define SDHI1_MSTP313 (1 << 13)
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#define SDHI2_MSTP312 (1 << 12)
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#define SD2CKCR 0xE6150078
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#define SD2_97500KHZ 0x7
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int board_early_init_f(void)
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{
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/* TMU0 */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/* SCIF0 */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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/* ETHER */
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
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/* eMMC */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
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/* SDHI0, 2 */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
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/*
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* SD0 clock is set to 97.5MHz by default.
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* Set SD2 to the 97.5MHz as well.
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*/
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writel(SD2_97500KHZ, SD2CKCR);
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return 0;
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}
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7790_pinmux_init();
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/* ETHER Enable */
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gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
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gpio_request(GPIO_FN_ETH_RX_ER, NULL);
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gpio_request(GPIO_FN_ETH_RXD0, NULL);
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gpio_request(GPIO_FN_ETH_RXD1, NULL);
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gpio_request(GPIO_FN_ETH_LINK, NULL);
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gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
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gpio_request(GPIO_FN_ETH_MDIO, NULL);
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gpio_request(GPIO_FN_ETH_TXD1, NULL);
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gpio_request(GPIO_FN_ETH_TX_EN, NULL);
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gpio_request(GPIO_FN_ETH_MAGIC, NULL);
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gpio_request(GPIO_FN_ETH_TXD0, NULL);
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gpio_request(GPIO_FN_ETH_MDC, NULL);
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gpio_request(GPIO_FN_IRQ0, NULL);
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gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */
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gpio_direction_output(GPIO_GP_5_31, 0);
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mdelay(20);
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gpio_set_value(GPIO_GP_5_31, 1);
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udelay(1);
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return 0;
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}
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#define CXR24 0xEE7003C0 /* MAC address high register */
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#define CXR25 0xEE7003C8 /* MAC address low register */
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int board_eth_init(bd_t *bis)
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{
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int ret = -ENODEV;
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#ifdef CONFIG_SH_ETHER
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u32 val;
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unsigned char enetaddr[6];
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ret = sh_eth_initialize(bis);
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if (!eth_getenv_enetaddr("ethaddr", enetaddr))
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return ret;
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/* Set Mac address */
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val = enetaddr[0] << 24 | enetaddr[1] << 16 |
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enetaddr[2] << 8 | enetaddr[3];
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writel(val, CXR24);
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val = enetaddr[4] << 8 | enetaddr[5];
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writel(val, CXR25);
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#endif
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return ret;
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}
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/* lager has KSZ8041NL/RNL */
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#define PHY_CONTROL1 0x1E
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#define PHY_LED_MODE 0xC0000
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#define PHY_LED_MODE_ACK 0x4000
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int board_phy_config(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
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ret &= ~PHY_LED_MODE;
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ret |= PHY_LED_MODE_ACK;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret = -ENODEV;
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#ifdef CONFIG_SH_MMCIF
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gpio_request(GPIO_FN_MMC1_D0, NULL);
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gpio_request(GPIO_FN_MMC1_D1, NULL);
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gpio_request(GPIO_FN_MMC1_D2, NULL);
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gpio_request(GPIO_FN_MMC1_D3, NULL);
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gpio_request(GPIO_FN_MMC1_D4, NULL);
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gpio_request(GPIO_FN_MMC1_D5, NULL);
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gpio_request(GPIO_FN_MMC1_D6, NULL);
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gpio_request(GPIO_FN_MMC1_D7, NULL);
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gpio_request(GPIO_FN_MMC1_CLK, NULL);
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gpio_request(GPIO_FN_MMC1_CMD, NULL);
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ret = mmcif_mmc_init();
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#endif
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#ifdef CONFIG_SH_SDHI
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gpio_request(GPIO_FN_SD0_DAT0, NULL);
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gpio_request(GPIO_FN_SD0_DAT1, NULL);
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gpio_request(GPIO_FN_SD0_DAT2, NULL);
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gpio_request(GPIO_FN_SD0_DAT3, NULL);
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gpio_request(GPIO_FN_SD0_CLK, NULL);
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gpio_request(GPIO_FN_SD0_CMD, NULL);
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gpio_request(GPIO_FN_SD0_CD, NULL);
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gpio_request(GPIO_FN_SD2_DAT0, NULL);
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gpio_request(GPIO_FN_SD2_DAT1, NULL);
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gpio_request(GPIO_FN_SD2_DAT2, NULL);
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gpio_request(GPIO_FN_SD2_DAT3, NULL);
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gpio_request(GPIO_FN_SD2_CLK, NULL);
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gpio_request(GPIO_FN_SD2_CMD, NULL);
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gpio_request(GPIO_FN_SD2_CD, NULL);
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/*
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* SDHI 0
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* need JP3 set to pin-1 side on board.
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*/
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gpio_request(GPIO_GP_5_24, NULL);
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gpio_request(GPIO_GP_5_29, NULL);
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gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
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gpio_direction_output(GPIO_GP_5_29, 1); /* 1: 3.3V, 0: 1.8V */
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
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SH_SDHI_QUIRK_16BIT_BUF);
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if (ret)
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return ret;
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/* SDHI 2 */
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gpio_request(GPIO_GP_5_25, NULL);
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gpio_request(GPIO_GP_5_30, NULL);
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gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
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gpio_direction_output(GPIO_GP_5_30, 1); /* 1: 3.3V, 0: 1.8V */
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
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#endif
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return ret;
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_RMOBILE_BOARD_STRING
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};
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void reset_cpu(ulong addr)
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{
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u8 val;
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i2c_set_bus_num(3); /* PowerIC connected to ch3 */
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i2c_init(400000, 0);
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i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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val |= 0x02;
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i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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}
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static const struct sh_serial_platdata serial_platdata = {
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.base = SCIF0_BASE,
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.type = PORT_SCIF,
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.clk = 14745600,
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.clk_mode = EXT_CLK,
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};
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U_BOOT_DEVICE(lager_serials) = {
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.name = "serial_sh",
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.platdata = &serial_platdata,
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};
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