upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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156 lines
5.1 KiB
156 lines
5.1 KiB
/*
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* MCF5227x Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __DSPI_H__
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#define __DSPI_H__
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/*********************************************************************
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* DMA Serial Peripheral Interface (DSPI)
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*********************************************************************/
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typedef struct dspi {
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u32 dmcr;
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u8 resv0[0x4];
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u32 dtcr;
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u32 dctar0;
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u32 dctar1;
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u32 dctar2;
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u32 dctar3;
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u32 dctar4;
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u32 dctar5;
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u32 dctar6;
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u32 dctar7;
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u32 dsr;
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u32 dirsr;
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u32 dtfr;
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u32 drfr;
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u32 dtfdr0;
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u32 dtfdr1;
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u32 dtfdr2;
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u32 dtfdr3;
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u8 resv1[0x30];
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u32 drfdr0;
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u32 drfdr1;
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u32 drfdr2;
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u32 drfdr3;
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} dspi_t;
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/* Bit definitions and macros for DMCR */
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#define DSPI_DMCR_HALT (0x00000001)
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#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
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#define DSPI_DMCR_CRXF (0x00000400)
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#define DSPI_DMCR_CTXF (0x00000800)
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#define DSPI_DMCR_DRXF (0x00001000)
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#define DSPI_DMCR_DTXF (0x00002000)
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#define DSPI_DMCR_CSIS0 (0x00010000)
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#define DSPI_DMCR_CSIS2 (0x00040000)
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#define DSPI_DMCR_CSIS3 (0x00080000)
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#define DSPI_DMCR_CSIS5 (0x00200000)
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#define DSPI_DMCR_ROOE (0x01000000)
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#define DSPI_DMCR_PCSSE (0x02000000)
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#define DSPI_DMCR_MTFE (0x04000000)
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#define DSPI_DMCR_FRZ (0x08000000)
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#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
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#define DSPI_DMCR_CSCK (0x40000000)
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#define DSPI_DMCR_MSTR (0x80000000)
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/* Bit definitions and macros for DTCR */
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#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for DCTAR group */
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#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
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#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
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#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
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#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
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#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
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#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
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#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
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#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
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#define DSPI_DCTAR_LSBFE (0x01000000)
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#define DSPI_DCTAR_CPHA (0x02000000)
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#define DSPI_DCTAR_CPOL (0x04000000)
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#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
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#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
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#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
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#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
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#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
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#define DSPI_DCTAR_PASC_1CLK (0x00000000)
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#define DSPI_DCTAR_PASC_3CLK (0x00100000)
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#define DSPI_DCTAR_PASC_5CLK (0x00200000)
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#define DSPI_DCTAR_PASC_7CLK (0x00300000)
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#define DSPI_DCTAR_PDT_1CLK (0x00000000)
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#define DSPI_DCTAR_PDT_3CLK (0x00040000)
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#define DSPI_DCTAR_PDT_5CLK (0x00080000)
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#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
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#define DSPI_DCTAR_PBR_1CLK (0x00000000)
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#define DSPI_DCTAR_PBR_3CLK (0x00010000)
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#define DSPI_DCTAR_PBR_5CLK (0x00020000)
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#define DSPI_DCTAR_PBR_7CLK (0x00030000)
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/* Bit definitions and macros for DSR */
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#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
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#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
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#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
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#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
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#define DSPI_DSR_RFDF (0x00020000)
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#define DSPI_DSR_RFOF (0x00080000)
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#define DSPI_DSR_TFFF (0x02000000)
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#define DSPI_DSR_TFUF (0x08000000)
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#define DSPI_DSR_EOQF (0x10000000)
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#define DSPI_DSR_TXRXS (0x40000000)
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#define DSPI_DSR_TCF (0x80000000)
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/* Bit definitions and macros for DIRSR */
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#define DSPI_DIRSR_RFDFS (0x00010000)
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#define DSPI_DIRSR_RFDFE (0x00020000)
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#define DSPI_DIRSR_RFOFE (0x00080000)
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#define DSPI_DIRSR_TFFFS (0x01000000)
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#define DSPI_DIRSR_TFFFE (0x02000000)
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#define DSPI_DIRSR_TFUFE (0x08000000)
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#define DSPI_DIRSR_EOQFE (0x10000000)
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#define DSPI_DIRSR_TCFE (0x80000000)
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/* Bit definitions and macros for DTFR */
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#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
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#define DSPI_DTFR_CS0 (0x00010000)
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#define DSPI_DTFR_CS2 (0x00040000)
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#define DSPI_DTFR_CS3 (0x00080000)
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#define DSPI_DTFR_CS5 (0x00200000)
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#define DSPI_DTFR_CTCNT (0x04000000)
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#define DSPI_DTFR_EOQ (0x08000000)
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#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
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#define DSPI_DTFR_CONT (0x80000000)
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/* Bit definitions and macros for DRFR */
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#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
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/* Bit definitions and macros for DTFDR group */
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#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
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#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for DRFDR group */
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#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
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#endif /* __DSPI_H__ */
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