upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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307 lines
12 KiB
307 lines
12 KiB
/*
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* (C) Copyright 2004 Sandburst Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
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* design.
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***********************************************************************/
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/*
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* $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
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#define CONFIG_440GX 1 /* Specifc GX support */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
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#undef CFG_DRAM_TEST /* Disable-takes long time!*/
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#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
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#define CONFIG_VERY_BIG_RAM 1
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
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#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
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#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
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#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
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#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
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#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000)
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#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000)
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#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
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/* Here for completeness */
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#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000)
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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#define CFG_TEMP_STACK_OCM 1
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#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
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#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SERIAL_MULTI 1
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#define CONFIG_BAUDRATE 9600
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* NVRAM/RTC
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*
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* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
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* The DS1743 code assumes this condition (i.e. -- it assumes the base
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* address for the RTC registers is:
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*
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* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
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*
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*----------------------------------------------------------------------*/
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#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
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#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
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#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C hardware support */
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#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
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#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
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#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
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#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
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#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
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#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
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#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
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#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*-----------------------------------------------------------------------
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* Networking
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*----------------------------------------------------------------------*/
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
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#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
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#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
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#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_HAS_ETH3
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
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#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
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#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
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#define CONFIG_PHY_RESET_DELAY 1000
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
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#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
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#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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/* Include NetConsole support */
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#define CONFIG_NETCONSOLE
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/* Include auto complete with tabs */
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#define CONFIG_AUTO_COMPLETE 1
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#define CFG_ALT_MEMTEST 1 /* use real memory test */
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
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#define CFG_PROMPT_HUSH_PS2 "> "
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/*-----------------------------------------------------------------------
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* Console Buffer
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*----------------------------------------------------------------------*/
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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/* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of cmd args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
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/*-----------------------------------------------------------------------
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* Memory Test
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*----------------------------------------------------------------------*/
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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/*-----------------------------------------------------------------------
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* Compact Flash (in true IDE mode)
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*----------------------------------------------------------------------*/
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#define CONFIG_IDE_RESET /* reset for ide supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
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#define CFG_ATA_BASE_ADDR 0xF0000000
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
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#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
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#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
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to get to the correct offset */
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#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
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/*-----------------------------------------------------------------------
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* PCI
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*----------------------------------------------------------------------*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
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#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT /* let board init pci target*/
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#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
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#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
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#define CFG_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
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#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
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#endif
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CFG_LOAD_ADDR 0x8000000 /* default load address */
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#define CFG_EXTBDINFO 1 /* use extended board_info */
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#define CFG_HZ 100 /* decr freq: 1 ms ticks */
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#endif /* __CONFIG_H */
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