upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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244 lines
7.5 KiB
244 lines
7.5 KiB
/*
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* 2004-2005 Gary Jennejohn <garyj@denx.de>
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*
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* Modified for the MP2USB by (C) Copyright 2005 Eric Benard
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* ebenard@eukrea.com
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*
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* Configuration settings for the MP2USB board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
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#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
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#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
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#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
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#define CONFIG_MP2USB 1 /* on an MP2USB Board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define USE_920T_MMU 1
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CFG_ATMEL_PLL_INIT_BUG 1
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define CFG_USE_MAIN_OSCILLATOR 1
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/* flash */
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#define MC_PUIA_VAL 0x00000000
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#define MC_PUP_VAL 0x00000000
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#define MC_PUER_VAL 0x00000000
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#define MC_ASR_VAL 0x00000000
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#define MC_AASR_VAL 0x00000000
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#define EBI_CFGR_VAL 0x00000000
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#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */
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#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */
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#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
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/* sdram */
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#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
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#define PIOC_BSR_VAL 0x00000000
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#define PIOC_PDR_VAL 0xFFFF0000
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#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
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#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */
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#define SDRAM 0x20000000 /* address of the SDRAM */
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#define SDRAM1 0x20000020 /* address of the SDRAM */
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#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
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#define SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define SDRC_MR_VAL1 0x00000004 /* refresh */
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#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_BAUDRATE 115200
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#define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
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/*
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* Hardware drivers
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*/
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/* define one of these to choose the DBGU, USART0 or USART1 as console */
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#define CONFIG_DBGU
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
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#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
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#define CONFIG_USB_OHCI 1
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#define CONFIG_USB_KEYBOARD 1
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_AT91C_PQFP_UHPBUG 1
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#undef CONFIG_HARD_I2C
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#ifdef CONFIG_HARD_I2C
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#define CFG_I2C_SPEED 0 /* not used */
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#define CFG_I2C_SLAVE 0 /* not used */
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#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
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#define CFG_I2C_RTC_ADDR 0x32
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#define CFG_I2C_EEPROM_ADDR 0x50
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW
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#endif
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/* still about 20 kB free with this defined */
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#define CFG_LONGHELP
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#define CONFIG_BOOTDELAY 3
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#if !defined(CONFIG_HARD_I2C)
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#define CONFIG_TIMESTAMP
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#endif
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SNTP
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#if defined(CONFIG_HARD_I2C)
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MISC
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#else
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_CACHE
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#undef CONFIG_CMD_AUTOSCRIPT
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_MISC
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#endif
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#define CFG_LONGHELP
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
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#define CFG_MEMTEST_START PHYS_SDRAM
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#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
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#define CONFIG_DRIVER_ETHER
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#define CONFIG_NET_RETRY_COUNT 20
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#undef CONFIG_AT91C_USE_RMII
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_SIZE 0x1000000 /* 16 megs main flash */
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 256
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#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
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#define CFG_FLASH_LOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Set Lock Bit */
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#define CFG_FLASH_UNLOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Clear Lock Bits */
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#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */
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#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_ENV_OFFSET)
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#define CFG_ENV_SIZE 0x20000
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#define CFG_LOAD_ADDR 0x21000000 /* default load address */
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#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_MAXARGS 32 /* max number of command args */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
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#define LITTLEENDIAN 1 /* used by usb_ohci.c */
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#ifndef __ASSEMBLY__
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/*-----------------------------------------------------------------------
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* Board specific extension for bd_info
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*
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* This structure is embedded in the global bd_info (bd_t) structure
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* and can be used by the board specific code (eg board/...)
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*/
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struct bd_info_ext {
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/* helper variable for board environment handling
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*
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* env_crc_valid == 0 => uninitialised
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* env_crc_valid > 0 => environment crc in flash is valid
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* env_crc_valid < 0 => environment crc in flash is invalid
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*/
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int env_crc_valid;
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};
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#endif /* __ASSEMBLY__ */
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#define CFG_HZ 1000
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#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
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/* AT91C_TC_TIMER_DIV1_CLOCK */
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ not supported
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#endif
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#define CFG_DEVICE_NULLDEV 1 /* enble null device */
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#undef CONFIG_SILENT_CONSOLE /* enable silent startup */
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#endif /* __CONFIG_H */
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