upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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108 lines
3.7 KiB
108 lines
3.7 KiB
/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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/* STM32F746 */
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#define ITCM_FLASH_BASE 0x00200000UL
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#define AXIM_FLASH_BASE 0x08000000UL
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#define ITCM_SRAM_BASE 0x00000000UL
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#define DTCM_SRAM_BASE 0x20000000UL
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#define SRAM1_BASE 0x20010000UL
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#define SRAM2_BASE 0x2004C000UL
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#define PERIPH_BASE 0x40000000UL
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#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
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#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000)
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#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000)
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#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000)
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#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000)
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#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
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#define USART2_BASE (APB1_PERIPH_BASE + 0x4400)
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#define USART3_BASE (APB1_PERIPH_BASE + 0x4800)
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#define PWR_BASE (APB1_PERIPH_BASE + 0x7000)
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#define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
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#define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
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#define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800)
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#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
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#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
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#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800)
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#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00)
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#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000)
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#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400)
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#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800)
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#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00)
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#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000)
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#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400)
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#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800)
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#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800)
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#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
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#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x40000140)
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static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
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[0 ... 3] = 32 * 1024,
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[4] = 128 * 1024,
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[5 ... 7] = 256 * 1024
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};
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#define STM32_BUS_MASK GENMASK(31, 16)
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struct stm32_rcc_regs {
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u32 cr; /* RCC clock control */
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u32 pllcfgr; /* RCC PLL configuration */
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u32 cfgr; /* RCC clock configuration */
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u32 cir; /* RCC clock interrupt */
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u32 ahb1rstr; /* RCC AHB1 peripheral reset */
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u32 ahb2rstr; /* RCC AHB2 peripheral reset */
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u32 ahb3rstr; /* RCC AHB3 peripheral reset */
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u32 rsv0;
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u32 apb1rstr; /* RCC APB1 peripheral reset */
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u32 apb2rstr; /* RCC APB2 peripheral reset */
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u32 rsv1[2];
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u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
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u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
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u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
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u32 rsv2;
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u32 apb1enr; /* RCC APB1 peripheral clock enable */
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u32 apb2enr; /* RCC APB2 peripheral clock enable */
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u32 rsv3[2];
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u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
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u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
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u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
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u32 rsv4;
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u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
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u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
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u32 rsv5[2];
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u32 bdcr; /* RCC Backup domain control */
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u32 csr; /* RCC clock control & status */
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u32 rsv6[2];
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u32 sscgr; /* RCC spread spectrum clock generation */
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u32 plli2scfgr; /* RCC PLLI2S configuration */
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u32 pllsaicfgr; /* PLLSAI configuration */
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u32 dckcfgr; /* dedicated clocks configuration register */
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};
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#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
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struct stm32_pwr_regs {
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u32 cr1; /* power control register 1 */
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u32 csr1; /* power control/status register 2 */
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u32 cr2; /* power control register 2 */
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u32 csr2; /* power control/status register 2 */
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};
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#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
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void stm32_flash_latency_cfg(int latency);
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#endif /* _ASM_ARCH_HARDWARE_H */
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