upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.2 KiB
149 lines
3.2 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pit.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/io.h>
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/*
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* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
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* setting the 20 bit counter period to its maximum (0xfffff).
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*/
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#define TIMER_LOAD_VAL 0xfffff
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#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
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#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
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#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
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#define TICKS_TO_USEC(ticks) ((ticks) / 6)
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ulong get_timer_masked(void);
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ulong resettime;
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/* nothing really to do with interrupts, just starts up a counter. */
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int timer_init(void)
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{
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/*
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* Enable PITC Clock
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* The clock is already enabled for system controller in boot
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*/
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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/* Enable PITC */
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at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
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reset_timer_masked();
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return 0;
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}
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/*
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* timer without interrupts
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*/
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static inline ulong get_timer_raw(void)
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{
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ulong now = READ_TIMER;
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if (now >= resettime)
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return now - resettime;
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else
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return 0xFFFFFFFFUL - (resettime - now) ;
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}
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void reset_timer_masked(void)
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{
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resettime = READ_TIMER;
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}
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ulong get_timer_masked(void)
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{
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return TICKS_TO_USEC(get_timer_raw());
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}
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void udelay_masked(unsigned long usec)
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{
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ulong tmp;
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tmp = get_timer(0);
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while (get_timer(tmp) < usec) /* our timer works in usecs */
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; /* NOP */
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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ulong now = get_timer_masked();
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if (now >= base)
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return now - base;
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else
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return TICKS_TO_USEC(0xFFFFFFFFUL) - (base - now) ;
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}
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void udelay(unsigned long usec)
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{
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udelay_masked(usec);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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ulong tbclk;
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tbclk = CFG_HZ;
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return tbclk;
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}
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/*
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* Reset the cpu by setting up the watchdog timer and let him time out.
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*/
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void reset_cpu(ulong ignored)
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{
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/* this is the way Linux does it */
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
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AT91_RSTC_PROCRST |
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AT91_RSTC_PERRST);
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while (1);
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/* Never reached */
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}
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