upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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375 lines
16 KiB
375 lines
16 KiB
/*
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* (C) Copyright 2004
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* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
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*
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* Support for the Elmeg VoVPN Gateway Module
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <asm/m8260_pci.h>
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#include <miiphy.h>
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#include "m88e6060.h"
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */
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/* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */
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/* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */
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/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */
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/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */
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/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */
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/* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
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/* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
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/* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
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/* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
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/* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
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/* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */
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/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */
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/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */
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/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */
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/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */
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/* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */
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/* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */
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/* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */
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/* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */
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/* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */
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/* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */
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/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
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/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
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/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
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/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
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/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
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/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
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/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
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/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
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/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
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/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */
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/* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */
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/* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */
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/* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */
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/* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */
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/* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */
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/* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */
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/* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */
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/* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */
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/* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */
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/* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */
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/* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */
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/* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */
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/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */
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/* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */
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/* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */
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/* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */
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/* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */
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/* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */
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/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */
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/* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */
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/* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */
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/* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */
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/* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */
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/* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */
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/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */
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/* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */
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/* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */
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/* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */
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/* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */
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/* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */
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/* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */
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/* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */
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/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */
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/* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */
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/* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */
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/* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */
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/* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */
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/* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
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/* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */
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/* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */
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/* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */
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/* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */
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/* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */
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/* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */
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/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
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}
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};
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void reset_phy (void)
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{
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volatile ioport_t *iop;
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#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)
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int i;
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unsigned short val;
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#endif
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iop = ioport_addr((immap_t *)CFG_IMMR, 0);
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/* Reset the PHY */
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iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */
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#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)
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udelay(20000);
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iop->pdat |= 0x00080000;
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for (i=0; i<100; i++) {
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udelay(20000);
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if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) {
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break;
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}
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}
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/* initialize switch */
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m88e6060_initialize( CFG_PHY_ADDR );
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#endif
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}
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static unsigned long UPMATable[] = {
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0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
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0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
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0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
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0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
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0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
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0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
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0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
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0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
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};
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int board_early_init_f (void)
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{
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volatile immap_t *immap;
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volatile memctl8260_t *memctl;
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volatile unsigned char *dummy;
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int i;
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immap = (immap_t *) CFG_IMMR;
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memctl = &immap->im_memctl;
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#if 0
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/* CS2-5 - DSP via UPMA */
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dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
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memctl->memc_mar = 0;
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memctl->memc_mamr = MxMR_OP_WARR;
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for (i = 0; i < 64; i++) {
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memctl->memc_mdr = UPMATable[i];
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*dummy = 0;
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}
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memctl->memc_mamr = 0x00044440;
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#else
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/* CS7 - DPRAM via UPMA */
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dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
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memctl->memc_mar = 0;
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memctl->memc_mamr = MxMR_OP_WARR;
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for (i = 0; i < 64; i++) {
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memctl->memc_mdr = UPMATable[i];
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*dummy = 0;
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}
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memctl->memc_mamr = 0x00044440;
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#endif
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return 0;
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}
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int misc_init_r (void)
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{
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volatile ioport_t *iop;
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unsigned char temp;
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#if 0
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/* DUMP UPMA RAM */
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volatile immap_t *immap;
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volatile memctl8260_t *memctl;
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volatile unsigned char *dummy;
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unsigned char c;
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int i;
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immap = (immap_t *) CFG_IMMR;
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memctl = &immap->im_memctl;
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dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
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memctl->memc_mar = 0;
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memctl->memc_mamr = MxMR_OP_RARR;
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for (i = 0; i < 64; i++) {
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c = *dummy;
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printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
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memctl->memc_mamr,
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memctl->memc_mar,
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memctl->memc_mdr );
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}
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memctl->memc_mamr = 0x00044440;
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#endif
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/* enable buffers (DSP, DPRAM) */
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iop = ioport_addr((immap_t *)CFG_IMMR, 0);
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iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */
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/* destroy DPRAM magic */
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*(volatile unsigned char *)0xf0500000 = 0x00;
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/* clear any pending DPRAM irq */
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temp = *(volatile unsigned char *)0xf05003ff;
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/* write module-id into DPRAM */
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*(volatile unsigned char *)0xf0500201 = 0x50;
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return 0;
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}
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#if defined(CONFIG_HAVE_OWN_RESET)
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int
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do_reset (void *cmdtp, int flag, int argc, char *argv[])
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{
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volatile ioport_t *iop;
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iop = ioport_addr((immap_t *)CFG_IMMR, 2);
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iop->pdat |= 0x00002000; /* PC18 = HW_RESET */
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return 1;
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}
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#endif /* CONFIG_HAVE_OWN_RESET */
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#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
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long int initdram (int board_type)
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{
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#ifndef CFG_RAMBOOT
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volatile immap_t *immap;
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volatile memctl8260_t *memctl;
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volatile uchar *ramaddr;
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int i;
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uchar c;
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immap = (immap_t *) CFG_IMMR;
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memctl = &immap->im_memctl;
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ramaddr = (uchar *) CFG_SDRAM_BASE;
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c = 0xff;
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immap->im_siu_conf.sc_ppc_acr = 0x02;
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immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
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immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
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immap->im_siu_conf.sc_tescr1 = 0x00000000;
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immap->im_siu_conf.sc_tescr2 = 0x00000000;
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memctl->memc_mptpr = CFG_MPTPR;
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memctl->memc_psrt = CFG_PSRT;
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM;
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/* Precharge all banks */
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memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
|
|
*ramaddr = c;
|
|
|
|
/* CBR refresh */
|
|
memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
|
|
for (i = 0; i < 8; i++)
|
|
*ramaddr = c;
|
|
|
|
/* Mode Register write */
|
|
memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
|
|
*ramaddr = c;
|
|
|
|
/* Refresh enable */
|
|
memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
|
|
*ramaddr = c;
|
|
#endif /* CFG_RAMBOOT */
|
|
|
|
return (CFG_SDRAM_SIZE);
|
|
}
|
|
|
|
int checkboard (void)
|
|
{
|
|
#ifdef CONFIG_CLKIN_66MHz
|
|
puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
|
|
#else
|
|
puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|