upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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404 lines
10 KiB
404 lines
10 KiB
/*
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* (C) Copyright 2001
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2001-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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#if (MPC8XX_SPEED <= 50000000L)
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
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0xFFFFFFFF,
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FE7F434, 0xEFABE834, 0x1FA7D435,
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
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0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
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0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
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#else
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
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0x1FF7F447,
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07,
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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#endif
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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*/
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int checkboard (void)
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{
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printf ("Board: Nexus NX823");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0, size_b1, size8, size9;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Up to 2 Banks of 64Mbit x 2 devices
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* Initial builds only have 1
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*/
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memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller SDRAM bank 0
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*/
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/*
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* Map controller SDRAM bank 1
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*/
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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/*
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* Perform SDRAM initializsation sequence
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*/
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memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
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udelay (1);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
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udelay (1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
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SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
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SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size_b0 = size9;
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
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} else { /* back to 8 columns */
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size_b0 = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
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}
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/*
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* Check Bank 1 Memory Size
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* use current column settings
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* [9 column SDRAM may also be used in 8 column mode,
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* but then only half the real size will be used.]
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*/
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size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type, both banks
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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udelay (1000);
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}
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/*
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* Final mapping: map bigger bank first
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*/
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if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
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memctl->memc_or2 =
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((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b0 > 0) {
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/*
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* Position Bank 0 immediately above Bank 1
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*/
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memctl->memc_or1 =
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((-size_b0) & 0xFFFF0000) |
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CFG_OR_TIMING_SDRAM;
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memctl->memc_br1 =
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((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
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BR_V)
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+ size_b1;
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} else {
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unsigned long reg;
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/*
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* No bank 0
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*
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* invalidate bank
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*/
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memctl->memc_br1 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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} else { /* SDRAM Bank 0 is bigger - map first */
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memctl->memc_or1 =
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((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br1 =
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(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b1 > 0) {
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/*
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* Position Bank 1 immediately above Bank 0
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*/
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memctl->memc_or2 =
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((-size_b1) & 0xFFFF0000) |
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CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
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BR_V)
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+ size_b0;
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} else {
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unsigned long reg;
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/*
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* No bank 1
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*
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* invalidate bank
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*/
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memctl->memc_br2 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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}
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udelay (10000);
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return (size_b0 + size_b1);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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u_long *my_sernum;
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int misc_init_r (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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char tmp[50];
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u_char *e = gd->bd->bi_enetaddr;
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/* save serial numbre from flash (uniquely programmed) */
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my_sernum = malloc (8);
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memcpy (my_sernum, gd->bd->bi_sernum, 8);
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/* save env variables according to sernum */
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sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
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setenv ("serial#", tmp);
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sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3],
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e[4], e[5]);
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setenv ("ethaddr", tmp);
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return (0);
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}
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void load_sernum_ethaddr (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int i;
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bd_t *bd = gd->bd;
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for (i = 0; i < 8; i++) {
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bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);
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}
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bd->bi_enetaddr[0] = 0x10;
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bd->bi_enetaddr[1] = 0x20;
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bd->bi_enetaddr[2] = 0x30;
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bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
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bd->bi_enetaddr[4] = bd->bi_sernum[5];
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bd->bi_enetaddr[5] = bd->bi_sernum[6];
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}
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