upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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140 lines
3.3 KiB
140 lines
3.3 KiB
/*
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* Copyright (C) 2010 Atmel Corporation
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*
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* Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spi.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hmatrix.h>
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#include <asm/arch/mmu.h>
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#include <asm/arch/portmux.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
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{
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/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
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.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
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.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
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.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
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| MMU_VMR_CACHE_NONE,
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}, {
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/* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
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.virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
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.nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
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.phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
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| MMU_VMR_CACHE_NONE,
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}, {
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/* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
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.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
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.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
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.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
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| MMU_VMR_CACHE_WRBACK,
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},
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};
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static const struct sdram_config sdram_config = {
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.data_bits = SDRAM_DATA_32BIT,
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.row_bits = 13,
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.col_bits = 10,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 7,
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.trp = 2,
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.trcd = 2,
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.tras = 5,
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.txsr = 6,
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/* 7.81 us */
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.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
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};
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
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| HMATRIX_BIT(EBI_NAND_ENABLE));
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portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
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PORTMUX_DRIVE_HIGH);
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portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
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PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
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| PORTMUX_DRIVE_MIN);
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portmux_enable_usart1(PORTMUX_DRIVE_MIN);
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#if defined(CONFIG_MACB)
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portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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#endif
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#if defined(CONFIG_MMC)
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portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
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#endif
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#if defined(CONFIG_ATMEL_SPI)
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portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
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#endif
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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unsigned long expected_size;
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unsigned long actual_size;
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void *sdram_base;
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sdram_base = uncached(EBI_SDRAM_BASE);
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expected_size = sdram_init(sdram_base, &sdram_config);
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actual_size = get_ram_size(sdram_base, expected_size);
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if (expected_size != actual_size)
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
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actual_size >> 20, expected_size >> 20);
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return actual_size;
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}
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int board_early_init_r(void)
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{
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gd->bd->bi_phy_id[0] = 0x01;
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gd->bd->bi_phy_id[1] = 0x03;
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bi)
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{
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macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
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macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
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return 0;
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}
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#endif
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
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}
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#endif /* CONFIG_ATMEL_SPI */
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