upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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44 lines
1.1 KiB
44 lines
1.1 KiB
/*
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* Register definitions for Parallel Input/Output Controller
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*/
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#ifndef __CPU_AT32AP_PIO2_H__
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#define __CPU_AT32AP_PIO2_H__
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/* PIO2 register offsets */
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#define PIO2_PER 0x0000
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#define PIO2_PDR 0x0004
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#define PIO2_PSR 0x0008
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#define PIO2_OER 0x0010
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#define PIO2_ODR 0x0014
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#define PIO2_OSR 0x0018
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#define PIO2_IFER 0x0020
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#define PIO2_IFDR 0x0024
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#define PIO2_ISFR 0x0028
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#define PIO2_SODR 0x0030
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#define PIO2_CODR 0x0034
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#define PIO2_ODSR 0x0038
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#define PIO2_PDSR 0x003c
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#define PIO2_IER 0x0040
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#define PIO2_IDR 0x0044
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#define PIO2_IMR 0x0048
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#define PIO2_ISR 0x004c
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#define PIO2_MDER 0x0050
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#define PIO2_MDDR 0x0054
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#define PIO2_MDSR 0x0058
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#define PIO2_PUDR 0x0060
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#define PIO2_PUER 0x0064
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#define PIO2_PUSR 0x0068
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#define PIO2_ASR 0x0070
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#define PIO2_BSR 0x0074
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#define PIO2_ABSR 0x0078
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#define PIO2_OWER 0x00a0
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#define PIO2_OWDR 0x00a4
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#define PIO2_OWSR 0x00a8
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/* Register access macros */
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#define pio2_readl(base,reg) \
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readl((void *)base + PIO2_##reg)
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#define pio2_writel(base,reg,value) \
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writel((value), (void *)base + PIO2_##reg)
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#endif /* __CPU_AT32AP_PIO2_H__ */
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