upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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70 lines
1.5 KiB
70 lines
1.5 KiB
/*
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __ARCH_BLACKFIN_CACHE_H
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#define __ARCH_BLACKFIN_CACHE_H
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#include <linux/linkage.h> /* for asmlinkage */
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/*
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* Bytes per L1 cache line
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* Blackfin loads 32 bytes for cache
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*/
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#ifdef CONFIG_SMP
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#define __cacheline_aligned
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#else
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#define ____cacheline_aligned
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/*
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* Put cacheline_aliged data to L1 data memory
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*/
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#ifdef CONFIG_CACHELINE_ALIGNED_L1
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#define __cacheline_aligned \
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__attribute__((__aligned__(L1_CACHE_BYTES), \
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__section__(".data_l1.cacheline_aligned")))
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#endif
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#endif
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/*
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* largest L1 which this arch supports
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*/
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#define L1_CACHE_SHIFT_MAX 5
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#if defined(CONFIG_SMP) && \
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!defined(CONFIG_BFIN_CACHE_COHERENT)
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# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
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# define __ARCH_SYNC_CORE_ICACHE
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# endif
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# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
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# define __ARCH_SYNC_CORE_DCACHE
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# endif
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#ifndef __ASSEMBLY__
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asmlinkage void __raw_smp_mark_barrier_asm(void);
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asmlinkage void __raw_smp_check_barrier_asm(void);
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static inline void smp_mark_barrier(void)
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{
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__raw_smp_mark_barrier_asm();
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}
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static inline void smp_check_barrier(void)
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{
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__raw_smp_check_barrier_asm();
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}
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void resync_core_dcache(void);
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void resync_core_icache(void);
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#endif
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#endif
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#endif
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