upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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455 lines
14 KiB
455 lines
14 KiB
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_PCI
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# include <pci.h>
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#endif
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void flash__init (void);
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void ether__init (void);
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void peripheral_power_enable (void);
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#if defined(CONFIG_SHOW_BOOT_PROGRESS)
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void show_boot_progress(int progress)
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{
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printf("Boot reached stage %d\n", progress);
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}
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#endif
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#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
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static inline void delay (unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* arch number of Integrator Board */
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gd->bd->bi_arch_number = 21;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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icache_enable ();
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flash__init ();
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return 0;
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}
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int misc_init_r (void)
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{
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#ifdef CONFIG_PCI
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pci_init();
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#endif
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setenv("verify", "n");
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return (0);
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifdef CONFIG_PCI
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_integrator_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ }
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};
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#endif
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// V3 access routines
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#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
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#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
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#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
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#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
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// Compute address necessary to access PCI config space for the given
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// bus and device.
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#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
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({ \
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unsigned int __address, __devicebit; \
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unsigned short __mapaddress; \
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unsigned int __dev = PCI_DEV(__devfn); /* FIXME to check!! (slot?) */ \
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\
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if (__bus == 0) { \
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/* local bus segment so need a type 0 config cycle */ \
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/* build the PCI configuration "address" with one-hot in A31-A11 */ \
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__address = PCI_CONFIG_BASE; \
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__address |= ((__devfn & 0x07) << 8); \
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__address |= __offset & 0xFF; \
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__mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \
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__devicebit = (1 << (__dev + 11)); \
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\
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if ((__devicebit & 0xFF000000) != 0) { \
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/* high order bits are handled by the MAP register */ \
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__mapaddress |= (__devicebit >> 16); \
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} else { \
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/* low order bits handled directly in the address */ \
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__address |= __devicebit; \
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} \
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} else { /* bus !=0 */ \
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/* not the local bus segment so need a type 1 config cycle */ \
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/* A31-A24 are don't care (so clear to 0) */ \
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__mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
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__address = PCI_CONFIG_BASE; \
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__address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
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__address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
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__address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number*/ \
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__address |= __offset & 0xFF; /* bits 7..0 = register number*/ \
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} \
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_V3Write16(V3_LB_MAP1, __mapaddress); \
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\
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__address; \
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})
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// _V3OpenConfigWindow - open V3 configuration window
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#define _V3OpenConfigWindow() \
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{ \
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/* Set up base0 to see all 512Mbytes of memory space (not */ \
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/* prefetchable), this frees up base1 for re-use by configuration*/ \
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/* memory */ \
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\
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_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
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0x90 | V3_LB_BASE_M_ENABLE)); \
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/* Set up base1 to point into configuration space, note that MAP1 */ \
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/* register is set up by pciMakeConfigAddress(). */ \
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\
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_V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \
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0x40 | V3_LB_BASE_M_ENABLE)); \
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}
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// _V3CloseConfigWindow - close V3 configuration window
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#define _V3CloseConfigWindow() \
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{ \
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/* Reassign base1 for use by prefetchable PCI memory */ \
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_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \
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| 0x84 | V3_LB_BASE_M_ENABLE)); \
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_V3Write16 (V3_LB_MAP1, \
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(((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \
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\
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/* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \
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\
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_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
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0x80 | V3_LB_BASE_M_ENABLE)); \
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}
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static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t dev,
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int offset, unsigned char *val)
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{
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_V3OpenConfigWindow();
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*val = *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
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_V3CloseConfigWindow();
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return 0;
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}
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static int pci_integrator_read__word(struct pci_controller *hose, pci_dev_t dev,
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int offset, unsigned short *val)
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{
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_V3OpenConfigWindow();
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*val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
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_V3CloseConfigWindow();
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return 0;
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}
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static int pci_integrator_read_dword(struct pci_controller *hose, pci_dev_t dev,
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int offset, unsigned int *val)
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{
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_V3OpenConfigWindow();
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*val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
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*val |= (*(volatile unsigned int *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset+2))) << 16;
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_V3CloseConfigWindow();
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return 0;
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}
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static int pci_integrator_write_byte(struct pci_controller *hose, pci_dev_t dev,
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int offset, unsigned char val)
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{
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_V3OpenConfigWindow();
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*(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
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_V3CloseConfigWindow();
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return 0;
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}
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static int pci_integrator_write_word(struct pci_controller *hose, pci_dev_t dev,
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int offset,unsigned short val)
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{
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_V3OpenConfigWindow();
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*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
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_V3CloseConfigWindow();
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return 0;
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}
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static int pci_integrator_write_dword(struct pci_controller *hose, pci_dev_t dev,
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int offset, unsigned int val)
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{
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_V3OpenConfigWindow();
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*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = (val & 0xFFFF);
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*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset + 2)) = ((val >> 16) & 0xFFFF);
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_V3CloseConfigWindow();
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return 0;
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}
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/******************************
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* PCI initialisation
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******************************/
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struct pci_controller integrator_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_integrator_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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volatile int i, j;
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struct pci_controller *hose = &integrator_hose;
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/* setting this register will take the V3 out of reset */
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*(volatile unsigned int *)(INTEGRATOR_SC_PCIENABLE) = 1;
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/* wait a few usecs to settle the device and the PCI bus */
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for (i = 0; i < 100 ; i++)
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j = i + 1;
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/* Now write the Base I/O Address Word to V3_BASE + 0x6C */
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*(volatile unsigned short *)(V3_BASE + V3_LB_IO_BASE) = (unsigned short)(V3_BASE >> 16);
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do {
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*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) = 0xAA;
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*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
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} while (*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||
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*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);
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/* Make sure that V3 register access is not locked, if it is, unlock it */
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if ((*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
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== V3_SYSTEM_M_LOCK)
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*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) = 0xA05F;
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/* Ensure that the slave accesses from PCI are disabled while we */
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/* setup windows */
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*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) &=
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~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
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/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
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*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;
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/* Make all accesses from PCI space retry until we're ready for them */
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*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;
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/* Set up any V3 PCI Configuration Registers that we absolutely have to */
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/* LB_CFG controls Local Bus protocol. */
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/* Enable LocalBus byte strobes for READ accesses too. */
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/* set bit 7 BE_IMODE and bit 6 BE_OMODE */
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*(volatile unsigned short *)(V3_BASE + V3_LB_CFG) |= 0x0C0;
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/* PCI_CMD controls overall PCI operation. */
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/* Enable PCI bus master. */
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*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) |= 0x04;
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/* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/
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*(volatile unsigned int *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |
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(V3_PCI_MAP_M_ADR_SIZE_512M |
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V3_PCI_MAP_M_REG_EN |
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V3_PCI_MAP_M_ENABLE);
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/* PCI_BASE0 is the PCI address of the start of the window */
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*(volatile unsigned int *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;
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/* PCI_MAP1 is LOCAL address of the start of the window */
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*(volatile unsigned int *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |
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(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |
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V3_PCI_MAP_M_ENABLE);
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/* PCI_BASE1 is the PCI address of the start of the window */
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*(volatile unsigned int *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;
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/* Set up the windows from local bus memory into PCI configuration, */
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/* I/O and Memory. */
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/* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
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*(volatile unsigned short *)(V3_BASE +V3_LB_BASE2) =
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((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
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*(volatile unsigned short *)(V3_BASE + V3_LB_MAP2) = 0;
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/* PCI Configuration, use LB_BASE1/LB_MAP1. */
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/* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
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/* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
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/* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
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*(volatile unsigned int *)(V3_BASE + V3_LB_BASE0) =
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INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
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*(volatile unsigned short *)(V3_BASE + V3_LB_MAP0) =
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((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
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/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
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*(volatile unsigned int *)(V3_BASE + V3_LB_BASE1) =
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INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
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*(volatile unsigned short *)(V3_BASE + V3_LB_MAP1) =
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(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
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/* Allow accesses to PCI Configuration space */
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/* and set up A1, A0 for type 1 config cycles */
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*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) =
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((*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG)) &
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~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |
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V3_PCI_CFG_M_AD_LOW0;
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/* now we can allow in PCI MEMORY accesses */
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*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) =
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(*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;
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/* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
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/* initialise and lock the V3 system register so that no one else */
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/* can play with it */
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*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
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(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;
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*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
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(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;
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/*
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* Register the hose
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*/
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space */
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pci_set_region(hose->regions + 0,
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0x00000000, 0x40000000, 0x01000000,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI Memory - config space */
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pci_set_region(hose->regions + 1,
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0x00000000, 0x62000000, 0x01000000,
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PCI_REGION_MEM);
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/* PCI V3 regs */
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pci_set_region(hose->regions + 2,
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0x00000000, 0x61000000, 0x00080000,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(hose->regions + 3,
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0x00000000, 0x60000000, 0x00010000,
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PCI_REGION_IO);
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pci_set_ops(hose,
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pci_integrator_read_byte,
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pci_integrator_read__word,
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pci_integrator_read_dword,
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pci_integrator_write_byte,
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pci_integrator_write_word,
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pci_integrator_write_dword);
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hose->region_count = 4;
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pci_register_hose(hose);
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pciauto_config_init(hose);
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pciauto_config_device(hose, 0);
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif
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/******************************
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Routine:
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Description:
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******************************/
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void flash__init (void)
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{
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}
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/*************************************************************
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Routine:ether__init
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Description: take the Ethernet controller out of reset and wait
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for the EEPROM load to complete.
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*************************************************************/
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void ether__init (void)
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{
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}
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|
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/******************************
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Routine:
|
|
Description:
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******************************/
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int dram_init (void)
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{
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return 0;
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}
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