upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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555 lines
21 KiB
555 lines
21 KiB
/*
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* (C) Copyright 2011
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* based on kilauea.h
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* by Stefan Roese, DENX Software Engineering, sr@denx.de.
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* and Grant Erickson <gerickson@nuovations.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/************************************************************************
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* io64.h - configuration for Guntermann & Drunck Io64 (405EX)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_IO64 1 /* Board is Io64 */
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#define CONFIG_405EX 1 /* Specifc 405EX support*/
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#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
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#endif
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/*
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* CHIP_21 errata
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*/
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#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME io64
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#define CONFIG_IDENT_STRING " io64 0.02"
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_MISC_INIT_R
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#define CONFIG_LAST_STAGE_INIT
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#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
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#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
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#define CONFIG_AUTOBOOT_STOP_STR " "
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/* new uImage format support */
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#define CONFIG_FIT
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#define CONFIG_FIT_VERBOSE
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_BASE 0xFC000000
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#define CONFIG_SYS_NVRAM_BASE 0xF0000000
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#define CONFIG_SYS_FPGA0_BASE 0xF0100000
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#define CONFIG_SYS_FPGA1_BASE 0xF0108000
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#define CONFIG_SYS_LATCH_BASE 0xF0200000
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/*-----------------------------------------------------------------------
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* Initial RAM & Stack Pointer Configuration Options
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*
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* There are traditionally three options for the primordial
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* (i.e. initial) stack usage on the 405-series:
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*
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* 1) On-chip Memory (OCM) (i.e. SRAM)
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* 2) Data cache
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* 3) SDRAM
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*
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* For the 405EX(r), there is no OCM, so we are left with (2) or (3)
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* the latter of which is less than desireable since it requires
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* setting up the SDRAM and ECC in assembly code.
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*
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* To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
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* select on the External Bus Controller (EBC) and then select a
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* value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
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* physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
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* select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
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* physical SDRAM to use (3).
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*-----------------------------------------------------------------------*/
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#define CONFIG_SYS_INIT_DCACHE_CS 4
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#if defined(CONFIG_SYS_INIT_DCACHE_CS)
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#define CONFIG_SYS_INIT_RAM_ADDR \
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(CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR \
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(CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
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#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
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#define CONFIG_SYS_INIT_RAM_SIZE \
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(4 << 10) /* 4 KiB */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* If the data cache is being used for the primordial stack and global
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* data area, the POST word must be placed somewhere else. The General
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* Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
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* its compare and mask register contents across reset, so it is used
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* for the POST word.
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*/
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#if defined(CONFIG_SYS_INIT_DCACHE_CS)
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# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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# define CONFIG_SYS_POST_WORD_ADDR \
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(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
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#else
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# define CONFIG_SYS_INIT_EXTRA_SIZE 16
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# define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
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# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
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#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#define CONFIG_SYS_BASE_BAUD 691200
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/* Gbit PHYs */
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
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#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
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#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
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#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
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#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
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#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
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/*
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* CONFIG_PPC4xx_DDR_AUTOCALIBRATION
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*
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* Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
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* SDRAM Controller DDR autocalibration values and takes a lot longer
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* to run than Method_B.
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* (See the Method_A and Method_B algorithm discription in the file:
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* arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
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* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
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*
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* DDR Autocalibration Method_B is the default.
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*/
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#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
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#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
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#undef CONFIG_PPC4xx_DDR_METHOD_A
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#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
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/* DDR1/2 SDRAM Device Control Register Data Values */
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#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
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SDRAM_RXBAS_SDSZ_128MB | \
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SDRAM_RXBAS_SDAM_MODE2 | \
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SDRAM_RXBAS_SDBE_ENABLE)
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#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
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#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
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#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
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#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
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SDRAM_MCOPT1_4_BANKS | \
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SDRAM_MCOPT1_DDR2_TYPE | \
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SDRAM_MCOPT1_QDEP | \
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SDRAM_MCOPT1_DCOO_DISABLED)
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#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
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#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
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SDRAM_MODT_EB0R_ENABLE)
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#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
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#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
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SDRAM_CODT_CKLZ_36OHM | \
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SDRAM_CODT_DQS_1_8_V_DDR2 | \
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SDRAM_CODT_IO_NMODE)
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#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
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#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(80) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
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#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(3) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
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#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
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#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
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SDRAM_INITPLR_IMA_ENCODE(0))
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#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
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JEDEC_MA_EMR_RTT_75OHM))
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#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
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JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
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JEDEC_MA_MR_BLEN_4 | \
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JEDEC_MA_MR_DLL_RESET))
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#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(3) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
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SDRAM_INITPLR_IBA_ENCODE(0x0) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
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#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
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JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
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JEDEC_MA_MR_BLEN_4))
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#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
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JEDEC_MA_EMR_RDQS_DISABLE | \
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JEDEC_MA_EMR_DQS_DISABLE | \
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JEDEC_MA_EMR_RTT_DISABLED | \
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JEDEC_MA_EMR_ODS_NORMAL))
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#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
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JEDEC_MA_EMR_RDQS_DISABLE | \
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JEDEC_MA_EMR_DQS_DISABLE | \
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JEDEC_MA_EMR_RTT_DISABLED | \
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JEDEC_MA_EMR_ODS_NORMAL))
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#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
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#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
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#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
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SDRAM_RQDC_RQFD_ENCODE(56))
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#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
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#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
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#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
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SDRAM_DLCR_DLCS_CONT_DONE | \
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SDRAM_DLCR_DLCV_ENCODE(165))
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#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
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#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
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#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
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SDRAM_SDTR1_RTW_2_CLK | \
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SDRAM_SDTR1_WTWO_1_CLK | \
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SDRAM_SDTR1_RTRO_1_CLK)
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#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
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SDRAM_SDTR2_WTR_2_CLK | \
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SDRAM_SDTR2_XSNR_32_CLK | \
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SDRAM_SDTR2_WPC_4_CLK | \
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SDRAM_SDTR2_RPC_2_CLK | \
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SDRAM_SDTR2_RP_3_CLK | \
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SDRAM_SDTR2_RRD_2_CLK)
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#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
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SDRAM_SDTR3_RC_ENCODE(12) | \
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SDRAM_SDTR3_XCS | \
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SDRAM_SDTR3_RFC_ENCODE(21))
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#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
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SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
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SDRAM_MMODE_BLEN_4)
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#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
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SDRAM_MEMODE_RTT_75OHM)
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
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#define CONFIG_PCA9698 1 /* NXP PCA9698 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C bootstrap EEPROM */
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
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#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
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/* Temp sensor/hwmon/dtt */
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#define CONFIG_DTT_LM63 1 /* National LM63 */
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#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */
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#define CONFIG_DTT_PWM_LOOKUPTABLE \
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{ { 40, 10 }, { 43, 13 }, { 46, 16 }, \
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{ 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
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#define CONFIG_DTT_TACH_LIMIT 0xa10
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/*-----------------------------------------------------------------------
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* Ethernet
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*----------------------------------------------------------------------*/
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#define CONFIG_M88E1111_PHY 1
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
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#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 0x13
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/* Debug messages for the DDR autocalibration */
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#define CONFIG_AUTOCALIB "silent\0"
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_PPC_OLD \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"logversion=2\0" \
|
|
"kernel_addr=fc000000\0" \
|
|
"fdt_addr=fc1e0000\0" \
|
|
"ramdisk_addr=fc200000\0" \
|
|
"pciconfighost=1\0" \
|
|
"pcie_mode=RP:RP\0" \
|
|
""
|
|
|
|
/*
|
|
* Commands additional to the ones defined in amcc-common.h
|
|
*/
|
|
#define CONFIG_CMD_CHIP_CONFIG
|
|
#define CONFIG_CMD_DTT
|
|
|
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#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
|
|
|
|
/* POST support */
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|
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
|
|
CONFIG_SYS_POST_CPU | \
|
|
CONFIG_SYS_POST_ETHER | \
|
|
CONFIG_SYS_POST_I2C | \
|
|
CONFIG_SYS_POST_MEMORY_ON | \
|
|
CONFIG_SYS_POST_UART)
|
|
|
|
/* Define here the base-addresses of the UARTs to test in POST */
|
|
#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
|
|
CONFIG_SYS_NS16550_COM2 }
|
|
|
|
#define CONFIG_LOGBUFFER
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|
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
|
|
|
|
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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|
|
|
/*-----------------------------------------------------------------------
|
|
* External Bus Controller (EBC) Setup
|
|
*----------------------------------------------------------------------*/
|
|
|
|
/* Memory Bank 0 (NOR-flash) */
|
|
#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
|
|
EBC_BXAP_TWT_ENCODE(11) | \
|
|
EBC_BXAP_BCE_DISABLE | \
|
|
EBC_BXAP_BCT_2TRANS | \
|
|
EBC_BXAP_CSN_ENCODE(0) | \
|
|
EBC_BXAP_OEN_ENCODE(0) | \
|
|
EBC_BXAP_WBN_ENCODE(1) | \
|
|
EBC_BXAP_WBF_ENCODE(2) | \
|
|
EBC_BXAP_TH_ENCODE(2) | \
|
|
EBC_BXAP_RE_DISABLED | \
|
|
EBC_BXAP_SOR_NONDELAYED | \
|
|
EBC_BXAP_BEM_WRITEONLY | \
|
|
EBC_BXAP_PEN_DISABLED)
|
|
#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
|
|
EBC_BXCR_BS_64MB | \
|
|
EBC_BXCR_BU_RW | \
|
|
EBC_BXCR_BW_16BIT)
|
|
|
|
/* Memory Bank 1 (NVRAM/Uart) */
|
|
#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
|
|
EBC_BXAP_FWT_ENCODE(8) | \
|
|
EBC_BXAP_BWT_ENCODE(4) | \
|
|
EBC_BXAP_BCE_DISABLE | \
|
|
EBC_BXAP_BCT_2TRANS | \
|
|
EBC_BXAP_CSN_ENCODE(0) | \
|
|
EBC_BXAP_OEN_ENCODE(1) | \
|
|
EBC_BXAP_WBN_ENCODE(1) | \
|
|
EBC_BXAP_WBF_ENCODE(1) | \
|
|
EBC_BXAP_TH_ENCODE(2) | \
|
|
EBC_BXAP_RE_DISABLED | \
|
|
EBC_BXAP_SOR_NONDELAYED | \
|
|
EBC_BXAP_BEM_WRITEONLY | \
|
|
EBC_BXAP_PEN_DISABLED)
|
|
#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
|
|
EBC_BXCR_BS_1MB | \
|
|
EBC_BXCR_BU_RW | \
|
|
EBC_BXCR_BW_8BIT)
|
|
|
|
/* Memory Bank 2 (FPGA) */
|
|
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
|
|
EBC_BXAP_TWT_ENCODE(5) | \
|
|
EBC_BXAP_BCE_DISABLE | \
|
|
EBC_BXAP_BCT_2TRANS | \
|
|
EBC_BXAP_CSN_ENCODE(0) | \
|
|
EBC_BXAP_OEN_ENCODE(2) | \
|
|
EBC_BXAP_WBN_ENCODE(1) | \
|
|
EBC_BXAP_WBF_ENCODE(1) | \
|
|
EBC_BXAP_TH_ENCODE(0) | \
|
|
EBC_BXAP_RE_DISABLED | \
|
|
EBC_BXAP_SOR_NONDELAYED | \
|
|
EBC_BXAP_BEM_WRITEONLY | \
|
|
EBC_BXAP_PEN_DISABLED)
|
|
#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
|
|
EBC_BXCR_BS_1MB | \
|
|
EBC_BXCR_BU_RW | \
|
|
EBC_BXCR_BW_16BIT)
|
|
|
|
/* Memory Bank 3 (Latches) */
|
|
#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
|
|
EBC_BXAP_FWT_ENCODE(8) | \
|
|
EBC_BXAP_BWT_ENCODE(4) | \
|
|
EBC_BXAP_BCE_DISABLE | \
|
|
EBC_BXAP_BCT_2TRANS | \
|
|
EBC_BXAP_CSN_ENCODE(0) | \
|
|
EBC_BXAP_OEN_ENCODE(1) | \
|
|
EBC_BXAP_WBN_ENCODE(1) | \
|
|
EBC_BXAP_WBF_ENCODE(1) | \
|
|
EBC_BXAP_TH_ENCODE(2) | \
|
|
EBC_BXAP_RE_DISABLED | \
|
|
EBC_BXAP_SOR_NONDELAYED | \
|
|
EBC_BXAP_BEM_WRITEONLY | \
|
|
EBC_BXAP_PEN_DISABLED)
|
|
#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
|
|
EBC_BXCR_BS_1MB | \
|
|
EBC_BXCR_BU_RW | \
|
|
EBC_BXCR_BW_16BIT)
|
|
|
|
/* EBC peripherals */
|
|
|
|
#define CONFIG_SYS_FPGA_BASE(k) \
|
|
(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
|
|
|
|
#define CONFIG_SYS_FPGA_DONE(k) \
|
|
(k ? 0x0040 : 0x0080)
|
|
|
|
#define CONFIG_SYS_FPGA_COUNT 2
|
|
|
|
#define CONFIG_SYS_FPGA_PTR { \
|
|
(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
|
|
(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
|
|
|
|
#define CONFIG_SYS_FPGA_COMMON
|
|
|
|
#define CONFIG_SYS_LATCH0_RESET 0xffff
|
|
#define CONFIG_SYS_LATCH0_BOOT 0xffff
|
|
#define CONFIG_SYS_LATCH1_RESET 0xffbf
|
|
#define CONFIG_SYS_LATCH1_BOOT 0xffff
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* GPIO Setup
|
|
*----------------------------------------------------------------------*/
|
|
#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \
|
|
{ \
|
|
/* GPIO Core 0 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
|
|
} \
|
|
}
|
|
|
|
#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
|
|
#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
|
|
|
|
#endif /* __CONFIG_H */
|
|
|