upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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83 lines
1.6 KiB
83 lines
1.6 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 Tuomas Tynkkynen
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*/
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#include <common.h>
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#include <fdtdec.h>
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region qemu_arm64_mem_map[] = {
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{
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/* Flash */
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Lowmem peripherals */
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.virt = 0x08000000UL,
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.phys = 0x08000000UL,
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.size = 0x38000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* RAM */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 255UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Highmem PCI-E ECAM memory area */
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.virt = 0x4010000000ULL,
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.phys = 0x4010000000ULL,
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.size = 0x10000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Highmem PCI-E MMIO memory area */
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.virt = 0x8000000000ULL,
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.phys = 0x8000000000ULL,
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.size = 0x8000000000ULL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = qemu_arm64_mem_map;
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#endif
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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void *board_fdt_blob_setup(void)
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{
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/* QEMU loads a generated DTB for us at the start of RAM. */
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return (void *)CONFIG_SYS_SDRAM_BASE;
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}
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