upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
1.0 KiB
61 lines
1.0 KiB
/* cache.S - low level cache handling routines
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* Copyright (C) 2003-2007 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/linkage.h>
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#include <config.h>
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#include <asm/blackfin.h>
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.text
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.align 2
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ENTRY(_blackfin_icache_flush_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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1:
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IFLUSH[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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IFLUSH[P0];
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SSYNC;
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RTS;
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ENDPROC(_blackfin_icache_flush_range)
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ENTRY(_blackfin_dcache_flush_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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1:
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FLUSH[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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FLUSH[P0];
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SSYNC;
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RTS;
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ENDPROC(_blackfin_dcache_flush_range)
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ENTRY(_blackfin_dcache_invalidate_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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1:
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FLUSHINV[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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/*
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* If the data crosses a cache line, then we'll be pointing to
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* the last cache line, but won't have flushed/invalidated it yet, so do
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* one more.
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*/
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FLUSHINV[P0];
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SSYNC;
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RTS;
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ENDPROC(_blackfin_dcache_invalidate_range)
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