upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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119 lines
3.5 KiB
119 lines
3.5 KiB
/*
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* Driver for ATMEL DataFlash support
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* Author : Hamid Ikdoumi (Atmel)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/hardware.h>
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#ifdef CONFIG_HAS_DATAFLASH
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#include <dataflash.h>
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/* Max Value = 10MHz to be compliant to the Continuous Array Read function */
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#define AT91C_SPI_CLK 10000000
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/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
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#define DATAFLASH_TCSS (0xFA << 16)
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#define DATAFLASH_TCHS (0x8 << 24)
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#define AT91C_TIMEOUT_WRDY 200000
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#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
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#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
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void AT91F_SpiInit(void)
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{
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/* Reset the SPI */
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AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST;
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/* Configure SPI in Master Mode with No CS selected !!! */
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AT91C_BASE_SPI0->SPI_MR =
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AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
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/* Configure CS0 */
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AT91C_BASE_SPI0->SPI_CSR[0] =
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AT91C_SPI_CPOL |
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(AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
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((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
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}
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void AT91F_SpiEnable(int cs)
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{
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switch (cs) {
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case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
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AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
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AT91C_BASE_SPI0->SPI_MR |=
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((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
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break;
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case 3:
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AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
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AT91C_BASE_SPI0->SPI_MR |=
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((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
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break;
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}
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/* SPI_Enable */
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AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN;
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}
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unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
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{
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unsigned int timeout;
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pDesc->state = BUSY;
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AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
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/* Initialize the Transmit and Receive Pointer */
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AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt;
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AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt;
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/* Intialize the Transmit and Receive Counters */
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AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size;
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AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size;
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if (pDesc->tx_data_size != 0) {
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/* Initialize the Next Transmit and Next Receive Pointer */
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AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt;
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AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt;
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/* Intialize the Next Transmit and Next Receive Counters */
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AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size;
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AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size;
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}
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked();
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timeout = 0;
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AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
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while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) &&
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((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
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AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
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pDesc->state = IDLE;
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if (timeout >= CFG_SPI_WRITE_TOUT) {
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printf("Error Timeout\n\r");
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return DATAFLASH_ERROR;
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}
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return DATAFLASH_OK;
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}
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#endif
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