upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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577 lines
17 KiB
577 lines
17 KiB
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_QE 1 /* Has QE */
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#define CONFIG_MPC83XX 1 /* MPC83XX family */
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#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
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#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
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/*
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* System Clock Setup
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*/
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#ifdef CONFIG_CLKIN_33MHZ
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#define CONFIG_83XX_CLKIN 33333333
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define PCI_33M 1
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#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
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#else
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#define CONFIG_83XX_CLKIN 66000000
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define PCI_66M 1
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#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
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#endif /* CONFIG_CLKIN_33MHZ */
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/*
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* Hardware Reset Configuration Word
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*/
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#define CFG_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_1X1 |\
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HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
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HRCWL_CORE_TO_CSB_2X1 |\
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HRCWL_CE_TO_PLL_1X15)
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#define CFG_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_PCICKDRV_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_SECONDARY_DDR_DISABLE |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LALE_EARLY)
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/*
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* System IO Config
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*/
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#define CFG_SICRH 0x00000000
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#define CFG_SICRL 0x40000000
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CONFIG_BOARD_EARLY_INIT_R
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/*
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* IMMR new address
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*/
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#define CFG_IMMR 0xE0000000
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/*
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* DDR Setup
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*/
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CFG_83XX_DDR_USES_CS0
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#define CONFIG_DDR_ECC /* support DDR ECC function */
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#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
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/*
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* DDRCDR - DDR Control Driver Register
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*/
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#define CFG_DDRCDR_VALUE 0x80080001
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#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
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/*
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* Manually set up DDR parameters
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*/
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#define CONFIG_DDR_II
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#define CFG_DDR_SIZE 256 /* MB */
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#define CFG_DDR_CS0_BNDS 0x0000000f
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#define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
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#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
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#define CFG_DDR_SDRAM_CFG2 0x00001000
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#define CFG_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CFG_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(1115 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CFG_DDR_MODE 0x47800432
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#define CFG_DDR_MODE2 0x8000c000
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#define CFG_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CFG_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \
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( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
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( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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( 3 << TIMING_CFG1_WRREC_SHIFT) | \
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(10 << TIMING_CFG1_REFREC_SHIFT) | \
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( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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( 3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CFG_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
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(0 << TIMING_CFG2_CPO_SHIFT))
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#define CFG_DDR_TIMING_3 0x00000000
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/*
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* Memory test
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*/
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00000000 /* memtest region */
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#define CFG_MEMTEST_END 0x00100000
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/*
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* The reserved memory
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*/
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_FLASH_BASE 0xFF800000 /* FLASH base address */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#else
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#undef CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
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#define CFG_LBC_LBCR 0x00000000
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/*
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* FLASH on the Local Bus
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*/
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#define CFG_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
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#define CFG_FLASH_PROTECTION 1 /* Use intel Flash protection. */
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
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#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
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#undef CFG_FLASH_CHECKSUM
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/*
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* NAND flash on the local bus
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*/
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#define CFG_NAND_BASE 0x60000000
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#define CONFIG_CMD_NAND 1
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#define CONFIG_NAND_FSL_UPM 1
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
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#define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
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/* Port size 8 bit, UPMA */
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#define CFG_BR1_PRELIM (CFG_NAND_BASE | 0x00000881)
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#define CFG_OR1_PRELIM 0xfc000001
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/*
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* Fujitsu MB86277 (MINT) graphics controller
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*/
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#define CFG_VIDEO_BASE 0x70000000
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#define CFG_LBLAWBAR2_PRELIM CFG_VIDEO_BASE
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#define CFG_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
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/* Port size 32 bit, UPMB */
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#define CFG_BR2_PRELIM (CFG_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
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#define CFG_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
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#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
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#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/* Pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_FSL_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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#define CFG_I2C2_OFFSET 0x3100
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_PCI
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#define CONFIG_83XX_GENERIC_PCI 1
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_MMIO_BASE 0x90000000
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#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
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#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_IO_BASE 0xE0300000
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#define CFG_PCI1_IO_PHYS 0xE0300000
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#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
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#ifdef CONFIG_PCI
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_UEC_ETH
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#define CONFIG_ETHPRIME "FSL UEC0"
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#define CONFIG_UEC_ETH1 /* GETH1 */
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#ifdef CONFIG_UEC_ETH1
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#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
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#define CFG_UEC1_RX_CLK QE_CLK_NONE
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#define CFG_UEC1_TX_CLK QE_CLK9
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#define CFG_UEC1_ETH_TYPE GIGA_ETH
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#define CFG_UEC1_PHY_ADDR 2
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#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
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#endif
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#define CONFIG_UEC_ETH2 /* GETH2 */
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#ifdef CONFIG_UEC_ETH2
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#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
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#define CFG_UEC2_RX_CLK QE_CLK_NONE
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#define CFG_UEC2_TX_CLK QE_CLK4
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#define CFG_UEC2_ETH_TYPE GIGA_ETH
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#define CFG_UEC2_PHY_ADDR 4
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#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
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#endif
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/*
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* Environment
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*/
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#ifndef CFG_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x20000
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#else /* CFG_RAMBOOT */
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#define CFG_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif /* CFG_RAMBOOT */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CFG_RAMBOOT)
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#undef CONFIG_CMD_ENV
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#undef CONFIG_CMD_LOADS
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Core HID Setup
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*/
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#define CFG_HID0_INIT 0x000000000
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#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
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#define CFG_HID2 HID2_HBE
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/*
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* MMU Setup
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*/
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR: cache cacheable */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT0L CFG_IBAT0L
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#define CFG_DBAT0U CFG_IBAT0U
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */
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#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
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#define CFG_DBAT1L CFG_IBAT1L
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#define CFG_DBAT1U CFG_IBAT1U
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/* NAND: cache-inhibit and guarded */
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#define CFG_IBAT2L (CFG_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
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BATL_GUARDEDSTORAGE)
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#define CFG_IBAT2U (CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
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#define CFG_DBAT2L CFG_IBAT2L
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#define CFG_DBAT2U CFG_IBAT2U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
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#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_DBAT3U CFG_IBAT3U
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/* Stack in dcache: cacheable, no memory coherence */
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#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10)
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#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CFG_DBAT4L CFG_IBAT4L
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#define CFG_DBAT4U CFG_IBAT4U
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#define CFG_IBAT5L (CFG_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CFG_IBAT5U (CFG_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
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#define CFG_DBAT5L CFG_IBAT5L
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#define CFG_DBAT5U CFG_IBAT5U
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#ifdef CONFIG_PCI
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/* PCI MEM space: cacheable */
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#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT6L CFG_IBAT6L
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#define CFG_DBAT6U CFG_IBAT6U
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/* PCI MMIO space: cache-inhibit and guarded */
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#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT7L CFG_IBAT7L
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#define CFG_DBAT7U CFG_IBAT7U
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#else /* CONFIG_PCI */
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#define CFG_IBAT6L (0)
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#define CFG_IBAT6U (0)
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#define CFG_IBAT7L (0)
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#define CFG_IBAT7U (0)
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#define CFG_DBAT6L CFG_IBAT6L
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#define CFG_DBAT6U CFG_IBAT6U
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#define CFG_DBAT7L CFG_IBAT7L
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#define CFG_DBAT7U CFG_IBAT7U
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#endif /* CONFIG_PCI */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_OVERWRITE
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|
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#if defined(CONFIG_UEC_ETH)
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_HAS_ETH3
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#define CONFIG_ETHADDR 00:04:9f:ef:01:01
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#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
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#define CONFIG_ETH2ADDR 00:04:9f:ef:01:03
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#define CONFIG_ETH3ADDR 00:04:9f:ef:01:04
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#endif
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|
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#define CONFIG_BAUDRATE 115200
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|
|
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#define CONFIG_LOADADDR a00000
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|
#define CONFIG_HOSTNAME mpc8360erdk
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|
#define CONFIG_BOOTFILE uImage
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|
|
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#define CONFIG_IPADDR 10.0.0.99
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#define CONFIG_SERVERIP 10.0.0.2
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#define CONFIG_GATEWAYIP 10.0.0.2
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|
#define CONFIG_NETMASK 255.255.255.0
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|
#define CONFIG_ROOTPATH /nfsroot/
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|
|
|
#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
|
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
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|
"netdev=eth0\0"\
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|
"consoledev=ttyS0\0"\
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|
"loadaddr=a00000\0"\
|
|
"fdtaddr=900000\0"\
|
|
"fdtfile=dtb\0"\
|
|
"fsfile=fs\0"\
|
|
"ubootfile=u-boot.bin\0"\
|
|
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
|
|
"setbootargs=setenv bootargs console=$consoledev,$baudrate "\
|
|
"$mtdparts panic=1\0"\
|
|
"adddhcpargs=setenv bootargs $bootargs ip=on\0"\
|
|
"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
|
|
"$gatewayip:$netmask:$hostname:$netdev:off "\
|
|
"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
|
|
"addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
|
|
"rootfstype=jffs2 rw\0"\
|
|
"tftp_get_uboot=tftp 100000 $ubootfile\0"\
|
|
"tftp_get_kernel=tftp $loadaddr $bootfile\0"\
|
|
"tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
|
|
"tftp_get_fs=tftp c00000 $fsfile\0"\
|
|
"nand_erase_kernel=nand erase 0 400000\0"\
|
|
"nand_erase_dtb=nand erase 400000 20000\0"\
|
|
"nand_erase_fs=nand erase 420000 3be0000\0"\
|
|
"nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
|
|
"nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
|
|
"nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
|
|
"nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
|
|
"nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
|
|
"nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
|
|
"cp.b 100000 ff800000 $filesize\0"\
|
|
"nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
|
|
"nand_write_kernel\0"\
|
|
"nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
|
|
"nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
|
|
"nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
|
|
"nand_reflash_fs\0"\
|
|
"boot_m=bootm $loadaddr - $fdtaddr\0"\
|
|
"dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
|
|
"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
|
|
"boot_m\0"\
|
|
"nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
|
|
"boot_m\0"\
|
|
""
|
|
|
|
#define CONFIG_BOOTCOMMAND "run dhcpboot"
|
|
|
|
#endif /* __CONFIG_H */
|
|
|