upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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240 lines
9.9 KiB
240 lines
9.9 KiB
/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*------------------------------------------------------------------------
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* BOARD/CPU
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*----------------------------------------------------------------------*/
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#define CONFIG_PK1C20 1 /* PK1C20 board */
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#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
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#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
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#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
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#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
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/*------------------------------------------------------------------------
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* CACHE -- the following will support II/s and II/f. The II/s does not
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* have dcache, so the cache instructions will behave as NOPs.
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*----------------------------------------------------------------------*/
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#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */
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#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */
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#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
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#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
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/*------------------------------------------------------------------------
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* MEMORY BASE ADDRESSES
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */
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#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
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#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
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#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
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#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
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#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
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/*------------------------------------------------------------------------
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* MEMORY ORGANIZATION
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* -Monitor at top.
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* -The heap is placed below the monitor.
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* -Global data is placed below the heap.
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* -The stack is placed below global data (&grows down).
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */
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#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
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#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
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#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
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/*------------------------------------------------------------------------
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* FLASH (AM29LV065D)
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*----------------------------------------------------------------------*/
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#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
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#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
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#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
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#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
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#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
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/*------------------------------------------------------------------------
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* ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
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* CFG_RESET_ADDR, since we assume the monitor is stored at the
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* reset address, no? This will keep the environment in user region
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* of flash. NOTE: the monitor length must be multiple of sector size
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* (which is common practice).
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*----------------------------------------------------------------------*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
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#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
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#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
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#define CONFIG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)
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/*------------------------------------------------------------------------
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* CONSOLE
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*----------------------------------------------------------------------*/
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#if defined(CONFIG_CONSOLE_JTAG)
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#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
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#else
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#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
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#endif
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#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
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#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
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#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
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#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
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/*------------------------------------------------------------------------
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* EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
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* epcs device access is enabled. The base address is the epcs
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* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
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* The register base is currently at offset 0x600 from the memory base.
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*----------------------------------------------------------------------*/
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#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
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/*------------------------------------------------------------------------
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* DEBUG
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*----------------------------------------------------------------------*/
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#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
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/*------------------------------------------------------------------------
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* TIMEBASE --
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*
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* The high res timer defaults to 1 msec. Since it includes the period
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* registers, we can slow it down to 10 msec using TMRCNT. If the default
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* period is acceptable, TMRCNT can be left undefined.
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*----------------------------------------------------------------------*/
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#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
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#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
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#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
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#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
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#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
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/*------------------------------------------------------------------------
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* STATUS LED -- Provides a simple blinking led. For Nios2 each board
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* must implement its own led routines -- leds are, after all,
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* board-specific, no?
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*----------------------------------------------------------------------*/
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#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
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#define CONFIG_STATUS_LED /* Enable status driver */
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#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
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#define STATUS_LED_STATE 1 /* Blinking */
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#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */
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/*------------------------------------------------------------------------
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* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
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* and really doesn't need any additional clutter. So I choose the lazy
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* way out to avoid changes there -- define the base address to ensure
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* cache bypass so there's no need to monkey with inx/outx macros.
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*----------------------------------------------------------------------*/
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#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
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#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
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#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
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#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.2.21
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#define CONFIG_SERVERIP 192.168.2.16
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_SAVES
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/*------------------------------------------------------------------------
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* COMPACT FLASH
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*----------------------------------------------------------------------*/
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#if defined(CONFIG_CMD_IDE)
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#define CONFIG_IDE_PREINIT /* Implement id_preinit */
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#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
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#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */
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#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
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#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
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#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */
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#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
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#define CFG_ATA_STRIDE 4 /* Width betwix addrs */
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#define CONFIG_DOS_PARTITION
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/* Board-specific cf regs */
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#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */
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#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/
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#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
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#endif
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/*------------------------------------------------------------------------
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* JFFS2
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*----------------------------------------------------------------------*/
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#if defined(CONFIG_CMD_JFFS2)
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#define CFG_JFFS_CUSTOM_PART /* board defined part */
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#endif
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/*------------------------------------------------------------------------
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* MISC
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*----------------------------------------------------------------------*/
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#define CFG_LONGHELP /* Provide extended help*/
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#define CFG_PROMPT "==> " /* Command prompt */
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#define CFG_CBSIZE 256 /* Console I/O buf size */
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#define CFG_MAXARGS 16 /* Max command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
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#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */
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#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
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#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif /* __CONFIG_H */
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