upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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400 lines
11 KiB
400 lines
11 KiB
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2004
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* (C) Copyright 2008
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#ifndef CFG_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
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(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
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__asm__ volatile ("sync");
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/* precharge all banks */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
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(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_EMODE));
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE,
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(SDRAM_MODE | 0x04000000));
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__asm__ volatile ("sync");
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#endif
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/* precharge all banks */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
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(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
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__asm__ volatile ("sync");
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/* auto refresh */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
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(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
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__asm__ volatile ("sync");
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/* set mode register */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_MODE));
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__asm__ volatile ("sync");
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/* normal operation */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
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(SDRAM_CONTROL | hi_addr_bit));
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__asm__ volatile ("sync");
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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phys_size_t initdram (int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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uint svr, pvr;
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
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__asm__ volatile ("sync");
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start (0);
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test1 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000);
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sdram_start(1);
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test2 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000);
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if (test1 > test2) {
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sdram_start (0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG,
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(0x13 + __builtin_ffs(dramsize >> 20) - 1));
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} else {
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
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}
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/* let SDRAM CS1 start right after CS0 */
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, (dramsize + 0x0000001c));/*512MB*/
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/* find RAM size using SDRAM CS1 only */
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if (!dramsize)
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sdram_start (0);
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test2 = test1 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
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if (!dramsize) {
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sdram_start (1);
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test2 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
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}
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if (test1 > test2) {
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sdram_start (0);
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dramsize2 = test1;
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} else {
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dramsize2 = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize2 < (1 << 20)) {
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dramsize2 = 0;
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}
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/* set SDRAM CS1 size according to the amount of RAM found */
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if (dramsize2 > 0) {
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG,
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(dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
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} else {
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
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}
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#else /* CFG_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
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if (dramsize2 >= 0x13) {
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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} else {
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dramsize2 = 0;
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}
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#endif /* CFG_RAMBOOT */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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svr = get_svr();
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pvr = get_pvr();
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if ((SVR_MJREV(svr) >= 2) &&
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(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
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out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
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__asm__ volatile ("sync");
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}
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return dramsize + dramsize2;
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}
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int checkboard (void)
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{
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puts ("Board: MUC.MC-52 HW WDT ");
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#if defined(CONFIG_HW_WATCHDOG)
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puts ("enabled\n");
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#else
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puts ("disabled\n");
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#endif
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return 0;
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}
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#ifdef CONFIG_PREBOOT
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static uchar kbd_magic_prefix[] = "key_magic";
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static uchar kbd_command_prefix[] = "key_cmd";
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#define S1_ROT 0xf0
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#define S2_Q 0x40
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#define S2_M 0x20
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struct kbd_data_t {
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char s1;
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char s2;
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};
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struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
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{
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kbd_data->s1 = in_8 ((volatile uchar*)CFG_STATUS1_BASE);
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kbd_data->s2 = in_8 ((volatile uchar*)CFG_STATUS2_BASE);
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return kbd_data;
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}
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static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
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{
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char s1 = str[0];
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char s2;
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if (s1 >= '0' && s1 <= '9')
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s1 -= '0';
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else if (s1 >= 'a' && s1 <= 'f')
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s1 = s1 - 'a' + 10;
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else if (s1 >= 'A' && s1 <= 'F')
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s1 = s1 - 'A' + 10;
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else
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return -1;
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if (((S1_ROT & kbd_data->s1) >> 4) != s1)
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return -1;
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s2 = (S2_Q | S2_M) & kbd_data->s2;
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switch (str[1]) {
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case 'q':
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case 'Q':
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if (s2 == S2_Q)
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return -1;
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break;
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case 'm':
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case 'M':
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if (s2 == S2_M)
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return -1;
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break;
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case '\0':
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if (s2 == (S2_Q | S2_M))
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return 0;
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default:
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return -1;
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}
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if (str[2])
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return -1;
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return 0;
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}
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static char *key_match (const struct kbd_data_t *kbd_data)
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{
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char magic[sizeof (kbd_magic_prefix) + 1];
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char *suffix;
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char *kbd_magic_keys;
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/*
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* The following string defines the characters that can be appended
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* to "key_magic" to form the names of environment variables that
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* hold "magic" key codes, i. e. such key codes that can cause
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* pre-boot actions. If the string is empty (""), then only
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* "key_magic" is checked (old behaviour); the string "125" causes
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* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
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*/
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if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
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kbd_magic_keys = "";
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/* loop over all magic keys;
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* use '\0' suffix in case of empty string
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*/
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for (suffix = kbd_magic_keys; *suffix ||
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suffix == kbd_magic_keys; ++suffix) {
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sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
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if (compare_magic(kbd_data, getenv(magic)) == 0) {
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char cmd_name[sizeof (kbd_command_prefix) + 1];
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char *cmd;
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sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
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cmd = getenv (cmd_name);
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return (cmd);
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}
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}
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return (NULL);
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}
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#endif /* CONFIG_PREBOOT */
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int misc_init_r (void)
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{
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#ifdef CONFIG_PREBOOT
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struct kbd_data_t kbd_data;
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/* Decode keys */
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char *str = strdup (key_match (get_keys (&kbd_data)));
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/* Set or delete definition */
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setenv ("preboot", str);
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free (str);
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#endif /* CONFIG_PREBOOT */
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' ');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' ');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' ');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' ');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' ');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' ');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' ');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' ');
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return 0;
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}
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int board_early_init_r (void)
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{
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out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
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out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CFG_FLASH_BASE));
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out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CFG_FLASH_BASE));
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out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
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STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE));
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out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
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STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE));
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return 0;
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}
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int last_stage_init (void)
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{
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5');
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out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2');
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return 0;
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}
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#if defined(CONFIG_HW_WATCHDOG)
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#define GPT_OUT_0 0x00000027
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#define GPT_OUT_1 0x00000037
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void hw_watchdog_reset (void)
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{
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/* Trigger HW Watchdog with TIMER_0 */
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out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_1);
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out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_0);
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}
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#endif
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init (struct pci_controller *);
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void pci_init_board (void)
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{
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pci_mpc5xxx_init (&hose);
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}
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#endif
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