upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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264 lines
7.7 KiB
264 lines
7.7 KiB
/*
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* Renesas RCar Gen2 PCIEC driver
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <pci.h>
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/* AHB-PCI Bridge PCI communication registers */
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#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
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#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
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#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
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#define RCAR_PCIAHB_PREFETCH0 0x0
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#define RCAR_PCIAHB_PREFETCH4 0x1
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#define RCAR_PCIAHB_PREFETCH8 0x2
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#define RCAR_PCIAHB_PREFETCH16 0x3
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#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
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#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
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#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
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#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
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#define RCAR_AHBPCI_WIN1_HOST BIT(30)
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#define RCAR_AHBPCI_WIN1_DEVICE BIT(31)
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#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
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#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
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#define RCAR_PCI_INT_SIGTABORT BIT(0)
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#define RCAR_PCI_INT_SIGRETABORT BIT(1)
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#define RCAR_PCI_INT_REMABORT BIT(2)
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#define RCAR_PCI_INT_PERR BIT(3)
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#define RCAR_PCI_INT_SIGSERR BIT(4)
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#define RCAR_PCI_INT_RESERR BIT(5)
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#define RCAR_PCI_INT_WIN1ERR BIT(12)
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#define RCAR_PCI_INT_WIN2ERR BIT(13)
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#define RCAR_PCI_INT_A BIT(16)
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#define RCAR_PCI_INT_B BIT(17)
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#define RCAR_PCI_INT_PME BIT(19)
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#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
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RCAR_PCI_INT_SIGRETABORT | \
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RCAR_PCI_INT_SIGRETABORT | \
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RCAR_PCI_INT_REMABORT | \
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RCAR_PCI_INT_PERR | \
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RCAR_PCI_INT_SIGSERR | \
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RCAR_PCI_INT_RESERR | \
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RCAR_PCI_INT_WIN1ERR | \
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RCAR_PCI_INT_WIN2ERR)
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#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
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#define RCAR_AHB_BUS_MMODE_HTRANS BIT(0)
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#define RCAR_AHB_BUS_MMODE_BYTE_BURST BIT(1)
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#define RCAR_AHB_BUS_MMODE_WR_INCR BIT(2)
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#define RCAR_AHB_BUS_MMODE_HBUS_REQ BIT(7)
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#define RCAR_AHB_BUS_SMODE_READYCTR BIT(17)
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#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
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RCAR_AHB_BUS_MMODE_BYTE_BURST | \
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RCAR_AHB_BUS_MMODE_WR_INCR | \
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RCAR_AHB_BUS_MMODE_HBUS_REQ | \
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RCAR_AHB_BUS_SMODE_READYCTR)
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#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
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#define RCAR_USBCTR_USBH_RST BIT(0)
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#define RCAR_USBCTR_PCICLK_MASK BIT(1)
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#define RCAR_USBCTR_PLL_RST BIT(2)
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#define RCAR_USBCTR_DIRPD BIT(8)
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#define RCAR_USBCTR_PCIAHB_WIN2_EN BIT(9)
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#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
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#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
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#define RCAR_PCI_ARBITER_PCIREQ0 BIT(0)
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#define RCAR_PCI_ARBITER_PCIREQ1 BIT(1)
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#define RCAR_PCI_ARBITER_PCIBP_MODE BIT(12)
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#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
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struct rcar_gen2_pci_priv {
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fdt_addr_t cfg_base;
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fdt_addr_t mem_base;
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};
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static int rcar_gen2_pci_addr_valid(pci_dev_t d, uint offset)
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{
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u32 slot;
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if (PCI_FUNC(d))
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return -EINVAL;
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/* Only one EHCI/OHCI device built-in */
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slot = PCI_DEV(d);
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if (slot > 2)
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return -EINVAL;
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/* bridge logic only has registers to 0x40 */
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if (slot == 0x0 && offset >= 0x40)
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return -EINVAL;
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return 0;
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}
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static u32 get_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
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{
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struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
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return priv->cfg_base + (PCI_DEV(bdf) >> 1) * 0x100 + (offset & ~3);
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}
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static u32 setup_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
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{
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struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
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u32 reg;
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reg = PCI_DEV(bdf) ? RCAR_AHBPCI_WIN1_DEVICE : RCAR_AHBPCI_WIN1_HOST;
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reg |= RCAR_AHBPCI_WIN_CTR_CFG;
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writel(reg, priv->cfg_base + RCAR_AHBPCI_WIN1_CTR_REG);
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return get_bus_address(dev, bdf, offset);
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}
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static int rcar_gen2_pci_read_config(struct udevice *dev, pci_dev_t bdf,
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uint offset, ulong *value,
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enum pci_size_t size)
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{
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u32 addr, reg;
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int ret;
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ret = rcar_gen2_pci_addr_valid(bdf, offset);
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if (ret) {
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*value = pci_get_ff(size);
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return 0;
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}
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addr = get_bus_address(dev, bdf, offset);
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reg = readl(addr);
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*value = pci_conv_32_to_size(reg, offset, size);
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return 0;
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}
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static int rcar_gen2_pci_write_config(struct udevice *dev, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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u32 addr, reg, old;
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int ret;
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ret = rcar_gen2_pci_addr_valid(bdf, offset);
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if (ret)
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return ret;
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addr = get_bus_address(dev, bdf, offset);
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old = readl(addr);
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reg = pci_conv_size_to_32(old, value, offset, size);
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writel(reg, addr);
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return 0;
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}
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static int rcar_gen2_pci_probe(struct udevice *dev)
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{
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struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
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struct clk pci_clk;
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u32 devad;
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int ret;
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ret = clk_get_by_index(dev, 0, &pci_clk);
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if (ret)
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return ret;
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ret = clk_enable(&pci_clk);
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if (ret)
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return ret;
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/* Clock & Reset & Direct Power Down */
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clrsetbits_le32(priv->cfg_base + RCAR_USBCTR_REG,
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RCAR_USBCTR_DIRPD | RCAR_USBCTR_PCICLK_MASK |
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RCAR_USBCTR_USBH_RST,
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RCAR_USBCTR_PCIAHB_WIN1_1G);
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clrbits_le32(priv->cfg_base + RCAR_USBCTR_REG, RCAR_USBCTR_PLL_RST);
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/* AHB-PCI Bridge Communication Registers */
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writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
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writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
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priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
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writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
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priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
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writel(priv->mem_base | RCAR_AHBPCI_WIN_CTR_MEM,
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priv->cfg_base + RCAR_AHBPCI_WIN2_CTR_REG);
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setbits_le32(priv->cfg_base + RCAR_PCI_ARBITER_CTR_REG,
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RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
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RCAR_PCI_ARBITER_PCIBP_MODE);
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/* PCI Configuration Registers for AHBPCI */
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devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
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writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
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writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
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writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
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writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
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devad + PCI_COMMAND);
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/* PCI Configuration Registers for OHCI */
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devad = setup_bus_address(dev, PCI_BDF(0, 1, 0), 0);
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writel(priv->mem_base + 0x0, devad + PCI_BASE_ADDRESS_0);
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writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
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devad + PCI_COMMAND);
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/* PCI Configuration Registers for EHCI */
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devad = setup_bus_address(dev, PCI_BDF(0, 2, 0), 0);
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writel(priv->mem_base + 0x1000, devad + PCI_BASE_ADDRESS_0);
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writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
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devad + PCI_COMMAND);
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/* Enable PCI interrupt */
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setbits_le32(priv->cfg_base + RCAR_PCI_INT_ENABLE_REG,
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RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME);
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return 0;
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}
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static int rcar_gen2_pci_ofdata_to_platdata(struct udevice *dev)
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{
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struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
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priv->cfg_base = devfdt_get_addr_index(dev, 0);
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priv->mem_base = devfdt_get_addr_index(dev, 1);
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if (!priv->cfg_base || !priv->mem_base)
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return -EINVAL;
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return 0;
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}
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static const struct dm_pci_ops rcar_gen2_pci_ops = {
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.read_config = rcar_gen2_pci_read_config,
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.write_config = rcar_gen2_pci_write_config,
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};
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static const struct udevice_id rcar_gen2_pci_ids[] = {
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{ .compatible = "renesas,pci-rcar-gen2" },
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{ }
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};
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U_BOOT_DRIVER(rcar_gen2_pci) = {
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.name = "rcar_gen2_pci",
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.id = UCLASS_PCI,
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.of_match = rcar_gen2_pci_ids,
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.ops = &rcar_gen2_pci_ops,
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.probe = rcar_gen2_pci_probe,
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.ofdata_to_platdata = rcar_gen2_pci_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct rcar_gen2_pci_priv),
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};
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