upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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568 lines
18 KiB
568 lines
18 KiB
/*
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* Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* The P2020COME board is only booted via the Freescale On-Chip ROM */
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_SYS_TEXT_BASE 0xf8f80000
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#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
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#ifdef CONFIG_SDCARD
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#define CONFIG_RAMBOOT_SDCARD 1
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RAMBOOT_SPIFLASH 1
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
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#define CONFIG_P2020 1
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#define CONFIG_P2020COME 1
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#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
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#define CONFIG_MP
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#define CONFIG_PCI 1 /* Enable PCI/PCIE */
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#if defined(CONFIG_PCI)
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#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
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#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#endif /* #if defined(CONFIG_PCI) */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_PCI)
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#define CONFIG_E1000 1 /* E1000 pci Ethernet card */
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#endif
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#ifndef __ASSEMBLY__
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extern unsigned long get_board_ddr_clk(unsigned long dummy);
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extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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/*
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* For P2020COME DDRCLK and SYSCLK are from the same oscillator
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* For DA phase the SYSCLK is 66MHz
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* For EA phase the SYSCLK is 100MHz
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*/
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
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#define CONFIG_HWCONFIG
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch prediction */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP 1
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x1fffffff
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
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#else
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#endif
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#define CONFIG_SYS_L2_SIZE (512 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
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+ CONFIG_SYS_L2_SIZE)
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_FSL_DDR3
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#define CONFIG_DDR_SPD
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#define CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
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#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
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#define CONFIG_SYS_DDR_SBE 0x00ff0000
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#define CONFIG_SYS_SPD_BUS_NUM 1
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#define SPD_EEPROM_ADDRESS 0x53
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
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* 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
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* 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
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* 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
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* 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
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* 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
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* 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
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*
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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/* There is no NOR Flash on P2020COME */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
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#define CONFIG_HWCONFIG
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
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/* the assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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#endif
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
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- GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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/*
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* Pass open firmware flat tree
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*/
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/* new uImage format support */
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#define CONFIG_FIT 1
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#define CONFIG_FIT_VERBOSE 1
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/* I2C */
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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/*
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* I2C2 EEPROM
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*/
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#define CONFIG_ID_EEPROM
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#ifdef CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#endif
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_FSL_ESPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#if defined(CONFIG_PCI)
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/* controller 3, Slot 3, tgtid 3, Base address 8000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, Slot 2, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, Slot 1, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#undef CONFIG_RTL8139
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#ifdef CONFIG_RTL8139
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/* This macro is used by RTL8139 but not defined in PPC architecture */
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#define KSEG1ADDR(x) (x)
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#define _IO_BASE 0x00000000
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#endif
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_DOS_PARTITION
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 2
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#define TSEC3_PHY_ADDR 1
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#undef CONFIG_VSC7385_ENET
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#if defined(CONFIG_RAMBOOT_SDCARD)
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#define CONFIG_ENV_IS_IN_MMC 1
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#define CONFIG_FSL_FIXED_MMC_LOCATION
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#elif defined(CONFIG_RAMBOOT_SPIFLASH)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_ENV_SPI_MODE 0
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_REGINFO
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PCI
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_MMC 1
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#ifdef CONFIG_MMC
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_CMD_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_FSL_ESDHC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
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#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
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#endif /* CONFIG_MMC */
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#define CONFIG_HAS_FSL_DR_USB
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#ifdef CONFIG_HAS_FSL_DR_USB
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#define CONFIG_USB_EHCI
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#ifdef CONFIG_USB_EHCI
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#define CONFIG_CMD_USB
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_USB_STORAGE
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#endif
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#endif
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#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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#endif
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/* Misc Extra Settings */
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#define CONFIG_CMD_DHCP 1
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#define CONFIG_CMD_DATE 1
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#define CONFIG_RTC_M41T62 1
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#define CONFIG_SYS_RTC_BUS_NUM 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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/* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
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#define CONFIG_SYS_BOOTM_LEN (64 << 20)
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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/* The mac addresses for all ethernet interface */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_HAS_ETH3
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#endif
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#define CONFIG_HOSTNAME unknown
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ecc=on\0" \
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"bootcmd=run sdboot\0" \
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"sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
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"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
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"$othbootargs; mmcinfo; " \
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"ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
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"ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
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"bootm $loadaddr - $fdtaddr\0" \
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|
"sdfatboot=setenv bootargs root=/dev/ram rw " \
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"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
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|
"$othbootargs; mmcinfo; " \
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|
"fatload mmc 0:1 $loadaddr $bootfile; " \
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"fatload mmc 0:1 $fdtaddr $fdtfile; " \
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|
"fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
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|
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
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|
"usbboot=setenv bootargs root=/dev/sda1 rw " \
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|
"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
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|
"$othbootargs; " \
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|
"usb start; " \
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|
"ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
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|
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
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|
"bootm $loadaddr - $fdtaddr\0" \
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|
"usbfatboot=setenv bootargs root=/dev/ram rw " \
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|
"console=$consoledev,$baudrate $othbootargs; " \
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|
"usb start; " \
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|
"fatload usb 0:2 $loadaddr $bootfile; " \
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|
"fatload usb 0:2 $fdtaddr $fdtfile; " \
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|
"fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
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|
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
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|
"usbext2boot=setenv bootargs root=/dev/ram rw " \
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|
"console=$consoledev,$baudrate $othbootargs; " \
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|
"usb start; " \
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|
"ext2load usb 0:4 $loadaddr $bootfile; " \
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|
"ext2load usb 0:4 $fdtaddr $fdtfile; " \
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|
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
|
"upgradespi=sf probe 0; " \
|
|
"setenv startaddr 0; " \
|
|
"setenv erasesize a0000; " \
|
|
"tftp 1000000 $tftppath/$uboot_spi; " \
|
|
"sf erase $startaddr $erasesize; " \
|
|
"sf write 1000000 $startaddr $filesize; " \
|
|
"sf erase 100000 120000\0" \
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|
"clearspienv=sf probe 0;sf erase 100000 20000\0" \
|
|
"othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
|
|
"netdev=eth0\0" \
|
|
"rootdelaysecond=15\0" \
|
|
"uboot_nor=u-boot-nor.bin\0" \
|
|
"uboot_spi=u-boot-p2020.spi\0" \
|
|
"uboot_sd=u-boot-p2020.bin\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=2000000\0" \
|
|
"ramdiskfile=rootfs-dev.ext2.img\0" \
|
|
"fdtaddr=c00000\0" \
|
|
"fdtfile=uImage-2.6.32-p2020.dtb\0" \
|
|
"tftppath=p2020\0"
|
|
|
|
#define CONFIG_HDBOOT \
|
|
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"usb start;" \
|
|
"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
|
|
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $tftppath/$bootfile;" \
|
|
"tftp $fdtaddr $tftppath/$fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
|
|
"tftp $loadaddr $tftppath/$bootfile;" \
|
|
"tftp $fdtaddr $tftppath/$fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
|
|
|
|
#endif /* __CONFIG_H */
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|
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