upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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451 lines
16 KiB
451 lines
16 KiB
/*
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* Copyright 2009-2010 eXMeritus, A Boeing Company
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* HardwareWall HWW-1U-1A airborne unit configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High-level system configuration options */
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#define CONFIG_BOOKE /* Power/PowerPC Book-E */
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#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */
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#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 family */
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#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */
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#define CONFIG_FSL_LAW /* FreeScale Local Access Window */
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#define CONFIG_P2020 /* FreeScale P2020 */
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#define CONFIG_HWW1U1A /* eXMeritus HardwareWall HWW-1U-1A */
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#define CONFIG_MP /* Multiprocessing support */
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#define CONFIG_HWCONFIG /* Use hwconfig from environment */
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#define CONFIG_L2_CACHE /* L2 cache enabled */
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#define CONFIG_BTB /* Branch predition enabled */
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#define CONFIG_PANIC_HANG /* No board reset on panic */
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#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r() */
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#define CONFIG_CMD_REGINFO /* Dump various CPU regs */
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/*
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* Allow the use of 36-bit physical addresses. Device-trees with 64-bit
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* addresses have known compatibility issues with some existing kernels.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
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/* Reserve plenty of RAM for malloc (we have 2GB+) */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
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/* How much L2 cache do we map so we can use it as RAM */
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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/* This is our temporary global data area just above the stack */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/* The stack grows down from the global data area */
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* Enable IRQs and watchdog with a 1000Hz system decrementer */
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#define CONFIG_CMD_IRQ
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#define CONFIG_SYS_HZ 1000
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/* -------------------------------------------------------------------- */
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/*
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* Clock crystal configuration:
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* (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
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* (2) CCB: Multiplier from SYS_CLK
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* (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
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*/
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#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
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#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
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/* -------------------------------------------------------------------- */
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM
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* 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1
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* 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused)
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* 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3
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* 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH
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* 0xe800_0000 0xefff_ffff 128M Spansion FLASH
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* 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0)
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* 0xffe0_0000 0xffef_ffff 1M CCSR
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* 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller
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*/
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/* Virtual Memory Map */
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_FLASH_BASE 0xe0000000
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
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#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/* Physical Memory Map */
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf /* for ASM code */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000 /* for ASM code */
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf /* for ASM code */
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000 /* for ASM code */
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/* -------------------------------------------------------------------- */
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/* U-Boot image (MONITOR_BASE == TEXT_BASE) */
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc /* Top address in flash */
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#define CONFIG_SYS_TEXT_BASE 0xeff80000 /* Start of U-Boot image */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN 0x80000 /* 512kB (4 flash sectors) */
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/*
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* U-Boot Environment Image: The two sectors immediately below U-Boot
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* form the U-Boot environment (regular and redundant).
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*/
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#define CONFIG_ENV_IS_IN_FLASH /* The environment image is stored in FLASH */
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#define CONFIG_ENV_OVERWRITE /* Allow "protected" variables to be erased */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (1 flash sector) */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
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/* Only use 8kB of each environment sector for data */
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#define CONFIG_ENV_SIZE 0x2000 /* 8kB */
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#define CONFIG_ENV_SIZE_REDUND 0x2000 /* 8kB */
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/* -------------------------------------------------------------------- */
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/* Serial Console Configuration */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* Echo back characters received during a serial download */
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#define CONFIG_LOADS_ECHO
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/* Allow a serial-download to temporarily change baud */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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/* -------------------------------------------------------------------- */
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/* PCI and PCI-Express Support */
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCI_PNP /* Scan PCI busses */
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#define CONFIG_CMD_PCI /* Enable the "pci" command */
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#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */
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#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */
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#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */
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#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */
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/* Enable 2 of the 3 PCI-E controllers */
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#define CONFIG_PCIE3
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#undef CONFIG_PCIE2
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#define CONFIG_PCIE1
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/* Display human-readable names when initializing */
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#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
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#define CONFIG_SYS_PCIE2_NAME "Unused"
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#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
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/*
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* PCI bus addresses
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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/* -------------------------------------------------------------------- */
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/* Generic FreeScale hardware I2C support */
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#define CONFIG_HARD_I2C
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#define CONFIG_FSL_I2C
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#define CONFIG_CMD_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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/* I2C bus configuration */
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS 0x51
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/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
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#define CONFIG_CMD_DATE
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_RTC_BUS_NUM 0
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/* Turn off RTC square-wave output to save battery */
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#define CONFIG_SYS_RTC_DS1337_NOOSC
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/* PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554) */
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#define CONFIG_PCA953X
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#define CONFIG_CMD_PCA953X
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#define CONFIG_CMD_PCA953X_INFO
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#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
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/* -------------------------------------------------------------------- */
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/* FreeScale DDR2/3 SDRAM Controller */
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#define CONFIG_FSL_DDR2 /* Our SDRAM slot is DDR2 */
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#define CONFIG_DDR_ECC /* Enable ECC by default */
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#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */
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#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */
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#define CONFIG_VERY_BIG_RAM /* Allow 2GB+ of RAM */
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#define CONFIG_CMD_SDRAM
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/* Standard P2020 DDR controller parameters */
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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/* Make sure to tell the DDR controller to preinitialze all of RAM */
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#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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/* -------------------------------------------------------------------- */
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/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
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/* Flash banks (2x 128MB) */
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#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
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#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_MAX_FLASH_SECT 1024
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#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
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/*
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* Flash access modes and timings (values are the defaults after a RESET).
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*
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* NOTE: These could probably be optimized but are more than sufficient for
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* this particular system for the moment.
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*/
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#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
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#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
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| OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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/* Configure both flash banks */
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#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
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#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
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#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
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#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
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/* Flash timeouts (in ms) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */
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/* Quiet flash testing */
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#define CONFIG_SYS_FLASH_QUIET_TEST
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/* Make program/erase count down from 45/5 (9....8....7....) */
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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/* -------------------------------------------------------------------- */
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/* Ethernet Device Support */
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#define CONFIG_MII /* Enable MII PHY code */
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#define CONFIG_MII_DEFAULT_TSEC /* ??? Copied from P2020DS */
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#define CONFIG_PHY_GIGE /* Support Gigabit PHYs */
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#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */
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/* Turn on various helpful networking commands */
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
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#define CONFIG_TSEC_ENET
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#define CONFIG_TSEC1
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#define CONFIG_TSEC2
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#define CONFIG_TSEC3
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#define CONFIG_TSEC1_NAME "owt0"
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#define CONFIG_TSEC2_NAME "owt1"
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#define CONFIG_TSEC3_NAME "peer"
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 3
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#define TSEC3_PHY_ADDR 4
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#define TSEC3_PHY_ADDR_CPUA 4
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#define TSEC3_PHY_ADDR_CPUB 5
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/* PCI-E dual-port E1000 (external ethernet ports) */
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#define CONFIG_E1000
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#define CONFIG_E1000_SPI
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#define CONFIG_E1000_SPI_GENERIC
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#define CONFIG_CMD_E1000
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/* We need the SPI infrastructure to poke the E1000's EEPROM */
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#define CONFIG_SPI
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#define CONFIG_SPI_X
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#define CONFIG_CMD_SPI
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#define MAX_SPI_BYTES 32
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/* -------------------------------------------------------------------- */
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/* USB Thumbdrive Device Support */
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_USB_STORAGE
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_CMD_USB
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/* Partition and Filesystem support */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_EFI_PARTITION
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#define CONFIG_ISO_PARTITION
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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/* -------------------------------------------------------------------- */
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/* Command line configuration. */
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#define CONFIG_CMDLINE_EDITING /* Enable command editing */
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#define CONFIG_COMMAND_HISTORY /* Enable command history */
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#define CONFIG_AUTO_COMPLETE /* Enable command completion */
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#define CONFIG_SYS_LONGHELP /* Enable detailed command help */
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#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */
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#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */
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#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */
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#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */
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#define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Command-line continuation */
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/* A little extra magic here for the prompt */
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#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
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#ifndef __ASSEMBLY__
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const char *hww1u1a_get_ps1(void);
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#endif
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/* Include a bunch of default commands we probably want */
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#include <config_cmd_default.h>
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/* Other helpful shell-like commands */
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#define CONFIG_MD5
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#define CONFIG_SHA1
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#define CONFIG_CMD_MD5SUM
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#define CONFIG_CMD_SHA1
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_SETEXPR
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/* -------------------------------------------------------------------- */
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/* Image manipulation and booting */
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/* We use the OpenFirmware-esque "Flattened Device Tree" */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_CMD_ELF
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB */
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/* This is the default address for commands with an optional address arg */
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#define CONFIG_LOADADDR 100000
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#define CONFIG_SYS_LOAD_ADDR 0x100000
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/* Test memory starting from the default load address to just below 2GB */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR
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#define CONFIG_SYS_MEMTEST_END 0x7f000000
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#define CONFIG_BOOTDELAY 20
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#define CONFIG_BOOTCOMMAND "echo Not yet flashed"
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#define CONFIG_BOOTARGS ""
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#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
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/* Extra environment parameters */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \
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"perf_mode=performance\0" \
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"hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
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"usb1:dr_mode=host,phy_type=ulpi\0" \
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"flkernel=0xe8020000\0" \
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"flinitramfs=0xe8800000\0" \
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"fldevicetree=0xeff20000\0" \
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"flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \
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"flboot=run preboot; run flbootm\0"
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#endif /* __CONFIG_H */
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